shaomiao.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 625 行 · 第 1/2 页
RPT
625 行
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 7/ 96( 7%) 0/ 48( 0%) 11/ 48( 22%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\111\shaomiao.rpt
shaomiao
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CP
Device-Specific Information: d:\111\shaomiao.rpt
shaomiao
** EQUATIONS **
CP : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d20 : INPUT;
d21 : INPUT;
d22 : INPUT;
d23 : INPUT;
d30 : INPUT;
d31 : INPUT;
d32 : INPUT;
d33 : INPUT;
d40 : INPUT;
d41 : INPUT;
d42 : INPUT;
d43 : INPUT;
-- Node name is ':28' = 'Q0'
-- Equation name is 'Q0', location is LC6_C18, type is buried.
Q0 = DFFE(!Q0, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':27' = 'Q1'
-- Equation name is 'Q1', location is LC3_C18, type is buried.
Q1 = DFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = Q0 & !Q1
# !Q0 & Q1;
-- Node name is ':26' = 'Q2'
-- Equation name is 'Q2', location is LC5_C18, type is buried.
Q2 = DFFE( _EQ002, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = !Q0 & Q2
# !Q1 & Q2
# Q0 & Q1 & !Q2;
-- Node name is 'SEGOUT0'
-- Equation name is 'SEGOUT0', type is output
SEGOUT0 = _LC1_C20;
-- Node name is 'SEGOUT1'
-- Equation name is 'SEGOUT1', type is output
SEGOUT1 = _LC2_C13;
-- Node name is 'SEGOUT2'
-- Equation name is 'SEGOUT2', type is output
SEGOUT2 = _LC5_C13;
-- Node name is 'SEGOUT3'
-- Equation name is 'SEGOUT3', type is output
SEGOUT3 = _LC2_C20;
-- Node name is 'SELOUT0'
-- Equation name is 'SELOUT0', type is output
SELOUT0 = _LC4_C18;
-- Node name is 'SELOUT1'
-- Equation name is 'SELOUT1', type is output
SELOUT1 = _LC7_C18;
-- Node name is 'SELOUT2'
-- Equation name is 'SELOUT2', type is output
SELOUT2 = _LC8_C18;
-- Node name is 'SELOUT3'
-- Equation name is 'SELOUT3', type is output
SELOUT3 = _LC1_C18;
-- Node name is ':171'
-- Equation name is '_LC4_C18', type is buried
_LC4_C18 = LCELL( _EQ003);
_EQ003 = Q0 & !Q1 & !Q2;
-- Node name is ':175'
-- Equation name is '_LC7_C18', type is buried
_LC7_C18 = LCELL( _EQ004);
_EQ004 = !Q0 & Q1 & !Q2;
-- Node name is ':179'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = LCELL( _EQ005);
_EQ005 = Q0 & Q1 & !Q2;
-- Node name is ':183'
-- Equation name is '_LC1_C18', type is buried
!_LC1_C18 = _LC1_C18~NOT;
_LC1_C18~NOT = LCELL( _EQ006);
_EQ006 = !Q2
# Q1
# Q0;
-- Node name is ':202'
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ007);
_EQ007 = d43 & !_LC8_C18
# !_LC1_C18 & !_LC8_C18
# d33 & _LC8_C18;
-- Node name is ':208'
-- Equation name is '_LC1_C13', type is buried
_LC1_C13 = LCELL( _EQ008);
_EQ008 = !_LC7_C18 & _LC8_C13
# d23 & _LC7_C18;
-- Node name is ':214'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = LCELL( _EQ009);
_EQ009 = _LC1_C13 & !_LC4_C18
# d13 & _LC4_C18;
-- Node name is ':223'
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ010);
_EQ010 = d42 & !_LC8_C18
# !_LC1_C18 & !_LC8_C18
# d32 & _LC8_C18;
-- Node name is ':226'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = LCELL( _EQ011);
_EQ011 = _LC6_C13 & !_LC7_C18
# d22 & _LC7_C18;
-- Node name is ':229'
-- Equation name is '_LC5_C13', type is buried
_LC5_C13 = LCELL( _EQ012);
_EQ012 = !_LC4_C18 & _LC7_C13
# d12 & _LC4_C18;
-- Node name is ':238'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ013);
_EQ013 = d41 & !_LC8_C18
# !_LC1_C18 & !_LC8_C18
# d31 & _LC8_C18;
-- Node name is ':241'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ014);
_EQ014 = _LC3_C13 & !_LC7_C18
# d21 & _LC7_C18;
-- Node name is ':244'
-- Equation name is '_LC2_C13', type is buried
_LC2_C13 = LCELL( _EQ015);
_EQ015 = _LC4_C13 & !_LC4_C18
# d11 & _LC4_C18;
-- Node name is ':253'
-- Equation name is '_LC2_C18', type is buried
_LC2_C18 = LCELL( _EQ016);
_EQ016 = d40 & !_LC8_C18
# !_LC1_C18 & !_LC8_C18
# d30 & _LC8_C18;
-- Node name is ':256'
-- Equation name is '_LC3_C20', type is buried
_LC3_C20 = LCELL( _EQ017);
_EQ017 = _LC2_C18 & !_LC7_C18
# d20 & _LC7_C18;
-- Node name is ':259'
-- Equation name is '_LC1_C20', type is buried
_LC1_C20 = LCELL( _EQ018);
_EQ018 = _LC3_C20 & !_LC4_C18
# d10 & _LC4_C18;
Project Information d:\111\shaomiao.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,553K
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