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📄 selling.rpt

📁 VHDL电子抢答器的实现。有多个文件
💻 RPT
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Device-Specific Information:                                d:\111\selling.rpt
selling

** EQUATIONS **

d10      : INPUT;
d11      : INPUT;
d12      : INPUT;
d13      : INPUT;
d20      : INPUT;
d21      : INPUT;
d22      : INPUT;
d23      : INPUT;
d30      : INPUT;
d31      : INPUT;
d32      : INPUT;
d33      : INPUT;
d40      : INPUT;
d41      : INPUT;
d42      : INPUT;
d43      : INPUT;
g10      : INPUT;
g11      : INPUT;
g12      : INPUT;
g13      : INPUT;
g20      : INPUT;
g21      : INPUT;
g22      : INPUT;
g23      : INPUT;
g30      : INPUT;
g31      : INPUT;
g32      : INPUT;
g33      : INPUT;
g40      : INPUT;
g41      : INPUT;
g42      : INPUT;
g43      : INPUT;
s0       : INPUT;
s1       : INPUT;

-- Node name is 'dw0' 
-- Equation name is 'dw0', type is output 
dw0      =  _LC1_C9;

-- Node name is 'dw1' 
-- Equation name is 'dw1', type is output 
dw1      =  _LC3_C9;

-- Node name is 'dw2' 
-- Equation name is 'dw2', type is output 
dw2      =  _LC7_B15;

-- Node name is 'dw3' 
-- Equation name is 'dw3', type is output 
dw3      =  _LC5_B15;

-- Node name is 'gw0' 
-- Equation name is 'gw0', type is output 
gw0      =  _LC1_C22;

-- Node name is 'gw1' 
-- Equation name is 'gw1', type is output 
gw1      =  _LC2_C22;

-- Node name is 'gw2' 
-- Equation name is 'gw2', type is output 
gw2      =  _LC3_A23;

-- Node name is 'gw3' 
-- Equation name is 'gw3', type is output 
gw3      =  _LC1_A23;

-- Node name is ':250' 
-- Equation name is '_LC7_A23', type is buried 
_LC7_A23 = LCELL( _EQ001);
  _EQ001 =  _LC6_A23
         #  g33 & !s0 &  s1;

-- Node name is ':252' 
-- Equation name is '_LC6_A23', type is buried 
_LC6_A23 = LCELL( _EQ002);
  _EQ002 =  _LC1_A23 & !s1
         #  g43 &  s0 &  s1;

-- Node name is ':262' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = LCELL( _EQ003);
  _EQ003 =  _LC8_A23
         #  g13 & !s0 & !s1;

-- Node name is ':264' 
-- Equation name is '_LC8_A23', type is buried 
_LC8_A23 = LCELL( _EQ004);
  _EQ004 =  _LC7_A23 &  s1
         #  g23 &  s0 & !s1;

-- Node name is ':271' 
-- Equation name is '_LC4_A23', type is buried 
_LC4_A23 = LCELL( _EQ005);
  _EQ005 =  _LC2_A23
         #  g32 & !s0 &  s1;

-- Node name is ':273' 
-- Equation name is '_LC2_A23', type is buried 
_LC2_A23 = LCELL( _EQ006);
  _EQ006 =  _LC3_A23 & !s1
         #  g42 &  s0 &  s1;

-- Node name is ':277' 
-- Equation name is '_LC3_A23', type is buried 
_LC3_A23 = LCELL( _EQ007);
  _EQ007 =  _LC5_A23
         #  g12 & !s0 & !s1;

-- Node name is ':279' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ008);
  _EQ008 =  _LC4_A23 &  s1
         #  g22 &  s0 & !s1;

-- Node name is ':286' 
-- Equation name is '_LC7_C22', type is buried 
_LC7_C22 = LCELL( _EQ009);
  _EQ009 =  _LC6_C22
         #  g31 & !s0 &  s1;

-- Node name is ':288' 
-- Equation name is '_LC6_C22', type is buried 
_LC6_C22 = LCELL( _EQ010);
  _EQ010 =  _LC2_C22 & !s1
         #  g41 &  s0 &  s1;

-- Node name is ':292' 
-- Equation name is '_LC2_C22', type is buried 
_LC2_C22 = LCELL( _EQ011);
  _EQ011 =  _LC8_C22
         #  g11 & !s0 & !s1;

-- Node name is ':294' 
-- Equation name is '_LC8_C22', type is buried 
_LC8_C22 = LCELL( _EQ012);
  _EQ012 =  _LC7_C22 &  s1
         #  g21 &  s0 & !s1;

-- Node name is ':301' 
-- Equation name is '_LC4_C22', type is buried 
_LC4_C22 = LCELL( _EQ013);
  _EQ013 =  _LC3_C22
         #  g30 & !s0 &  s1;

-- Node name is ':303' 
-- Equation name is '_LC3_C22', type is buried 
_LC3_C22 = LCELL( _EQ014);
  _EQ014 =  _LC1_C22 & !s1
         #  g40 &  s0 &  s1;

-- Node name is ':307' 
-- Equation name is '_LC1_C22', type is buried 
_LC1_C22 = LCELL( _EQ015);
  _EQ015 =  _LC5_C22
         #  g10 & !s0 & !s1;

-- Node name is ':309' 
-- Equation name is '_LC5_C22', type is buried 
_LC5_C22 = LCELL( _EQ016);
  _EQ016 =  _LC4_C22 &  s1
         #  g20 &  s0 & !s1;

-- Node name is ':316' 
-- Equation name is '_LC6_B15', type is buried 
_LC6_B15 = LCELL( _EQ017);
  _EQ017 =  _LC4_B15
         #  d33 & !s0 &  s1;

-- Node name is ':318' 
-- Equation name is '_LC4_B15', type is buried 
_LC4_B15 = LCELL( _EQ018);
  _EQ018 =  _LC5_B15 & !s1
         #  d43 &  s0 &  s1;

-- Node name is ':322' 
-- Equation name is '_LC5_B15', type is buried 
_LC5_B15 = LCELL( _EQ019);
  _EQ019 =  _LC8_B15
         #  d13 & !s0 & !s1;

-- Node name is ':324' 
-- Equation name is '_LC8_B15', type is buried 
_LC8_B15 = LCELL( _EQ020);
  _EQ020 =  _LC6_B15 &  s1
         #  d23 &  s0 & !s1;

-- Node name is ':331' 
-- Equation name is '_LC2_B15', type is buried 
_LC2_B15 = LCELL( _EQ021);
  _EQ021 =  _LC1_B15
         #  d32 & !s0 &  s1;

-- Node name is ':333' 
-- Equation name is '_LC1_B15', type is buried 
_LC1_B15 = LCELL( _EQ022);
  _EQ022 =  _LC7_B15 & !s1
         #  d42 &  s0 &  s1;

-- Node name is ':337' 
-- Equation name is '_LC7_B15', type is buried 
_LC7_B15 = LCELL( _EQ023);
  _EQ023 =  _LC3_B15
         #  d12 & !s0 & !s1;

-- Node name is ':339' 
-- Equation name is '_LC3_B15', type is buried 
_LC3_B15 = LCELL( _EQ024);
  _EQ024 =  _LC2_B15 &  s1
         #  d22 &  s0 & !s1;

-- Node name is ':346' 
-- Equation name is '_LC7_C9', type is buried 
_LC7_C9  = LCELL( _EQ025);
  _EQ025 =  _LC6_C9
         #  d31 & !s0 &  s1;

-- Node name is ':348' 
-- Equation name is '_LC6_C9', type is buried 
_LC6_C9  = LCELL( _EQ026);
  _EQ026 =  _LC3_C9 & !s1
         #  d41 &  s0 &  s1;

-- Node name is ':352' 
-- Equation name is '_LC3_C9', type is buried 
_LC3_C9  = LCELL( _EQ027);
  _EQ027 =  _LC8_C9
         #  d11 & !s0 & !s1;

-- Node name is ':354' 
-- Equation name is '_LC8_C9', type is buried 
_LC8_C9  = LCELL( _EQ028);
  _EQ028 =  _LC7_C9 &  s1
         #  d21 &  s0 & !s1;

-- Node name is ':361' 
-- Equation name is '_LC4_C9', type is buried 
_LC4_C9  = LCELL( _EQ029);
  _EQ029 =  _LC2_C9
         #  d30 & !s0 &  s1;

-- Node name is ':363' 
-- Equation name is '_LC2_C9', type is buried 
_LC2_C9  = LCELL( _EQ030);
  _EQ030 =  _LC1_C9 & !s1
         #  d40 &  s0 &  s1;

-- Node name is ':367' 
-- Equation name is '_LC1_C9', type is buried 
_LC1_C9  = LCELL( _EQ031);
  _EQ031 =  _LC5_C9
         #  d10 & !s0 & !s1;

-- Node name is ':369' 
-- Equation name is '_LC5_C9', type is buried 
_LC5_C9  = LCELL( _EQ032);
  _EQ032 =  _LC4_C9 &  s1
         #  d20 &  s0 & !s1;



Project Information                                         d:\111\selling.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,933K

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