📄 selling.rpt
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Project Information d:\111\selling.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 12/12/2004 18:20:37
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SELLING
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
selling EPF10K10LC84-3 34 8 0 0 0 % 32 5 %
User Pins: 34 8 0
Device-Specific Information: d:\111\selling.rpt
selling
***** Logic for device 'selling' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
^
C
R R R R R R R R R R R O
E E E E E E E E E E E N
S S S S S S S V S G S S S F
E E E E E E E C E N E E E _ ^
R R R R R R R C R D R R R # D n
V V V V V V V I V d d g I V V V g T O C
E E E E E E E N E s 2 3 4 N E E E 1 C N E
D D D D D D D T D 1 0 0 0 T D D D 1 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | gw3
^nCE | 14 72 | gw2
#TDI | 15 71 | g43
g32 | 16 70 | g33
g22 | 17 69 | g23
g42 | 18 68 | GNDINT
g13 | 19 67 | d22
VCCINT | 20 66 | d33
d23 | 21 65 | dw3
d43 | 22 EPF10K10LC84-3 64 | dw2
d13 | 23 63 | VCCINT
d42 | 24 62 | gw0
d12 | 25 61 | g31
GNDINT | 26 60 | g20
g41 | 27 59 | g30
dw1 | 28 58 | d11
g21 | 29 57 | #TMS
d21 | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | gw1
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ d R R d d V G s d d V G g d R R R R g
C n 4 E E w 3 C N 0 1 4 C N 1 3 E E E E 1
C C 1 S S 0 1 C D 0 0 C D 0 2 S S S S 2
I O E E I I I I E E E E
N N R R N N N N R R R R
T F V V T T T T V V V V
I E E E E E E
G D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\111\selling.rpt
selling
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
B15 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/22( 45%)
C9 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
C22 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 10/22( 45%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 36/53 ( 67%)
Total logic cells used: 32/576 ( 5%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 4.00/4 (100%)
Total fan-in: 128/2304 ( 5%)
Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 32
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 8/0
C: 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 16/0
Total: 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 8 0 0 0 0 0 0 8 8 0 32/0
Device-Specific Information: d:\111\selling.rpt
selling
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - -- INPUT 0 0 0 1 d10
58 - - C -- INPUT 0 0 0 1 d11
25 - - B -- INPUT 0 0 0 1 d12
23 - - B -- INPUT 0 0 0 1 d13
1 - - - -- INPUT 0 0 0 1 d20
30 - - C -- INPUT 0 0 0 1 d21
67 - - B -- INPUT 0 0 0 1 d22
21 - - B -- INPUT 0 0 0 1 d23
84 - - - -- INPUT 0 0 0 1 d30
39 - - - 11 INPUT 0 0 0 1 d31
48 - - - 15 INPUT 0 0 0 1 d32
66 - - B -- INPUT 0 0 0 1 d33
44 - - - -- INPUT 0 0 0 1 d40
35 - - - 06 INPUT 0 0 0 1 d41
24 - - B -- INPUT 0 0 0 1 d42
22 - - B -- INPUT 0 0 0 1 d43
47 - - - 14 INPUT 0 0 0 1 g10
78 - - - 24 INPUT 0 0 0 1 g11
53 - - - 20 INPUT 0 0 0 1 g12
19 - - A -- INPUT 0 0 0 1 g13
60 - - C -- INPUT 0 0 0 1 g20
29 - - C -- INPUT 0 0 0 1 g21
17 - - A -- INPUT 0 0 0 1 g22
69 - - A -- INPUT 0 0 0 1 g23
59 - - C -- INPUT 0 0 0 1 g30
61 - - C -- INPUT 0 0 0 1 g31
16 - - A -- INPUT 0 0 0 1 g32
70 - - A -- INPUT 0 0 0 1 g33
83 - - - 13 INPUT 0 0 0 1 g40
27 - - C -- INPUT 0 0 0 1 g41
18 - - A -- INPUT 0 0 0 1 g42
71 - - A -- INPUT 0 0 0 1 g43
42 - - - -- INPUT 0 0 0 32 s0
2 - - - -- INPUT 0 0 0 32 s1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\111\selling.rpt
selling
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
38 - - - 10 OUTPUT 0 1 0 0 dw0
28 - - C -- OUTPUT 0 1 0 0 dw1
64 - - B -- OUTPUT 0 1 0 0 dw2
65 - - B -- OUTPUT 0 1 0 0 dw3
62 - - C -- OUTPUT 0 1 0 0 gw0
54 - - - 21 OUTPUT 0 1 0 0 gw1
72 - - A -- OUTPUT 0 1 0 0 gw2
73 - - A -- OUTPUT 0 1 0 0 gw3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\111\selling.rpt
selling
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 23 OR2 3 1 0 1 :250
- 6 - A 23 OR2 3 1 0 1 :252
- 1 - A 23 OR2 3 1 1 1 :262
- 8 - A 23 OR2 3 1 0 1 :264
- 4 - A 23 OR2 3 1 0 1 :271
- 2 - A 23 OR2 3 1 0 1 :273
- 3 - A 23 OR2 3 1 1 1 :277
- 5 - A 23 OR2 3 1 0 1 :279
- 7 - C 22 OR2 3 1 0 1 :286
- 6 - C 22 OR2 3 1 0 1 :288
- 2 - C 22 OR2 3 1 1 1 :292
- 8 - C 22 OR2 3 1 0 1 :294
- 4 - C 22 OR2 3 1 0 1 :301
- 3 - C 22 OR2 3 1 0 1 :303
- 1 - C 22 OR2 3 1 1 1 :307
- 5 - C 22 OR2 3 1 0 1 :309
- 6 - B 15 OR2 3 1 0 1 :316
- 4 - B 15 OR2 3 1 0 1 :318
- 5 - B 15 OR2 3 1 1 1 :322
- 8 - B 15 OR2 3 1 0 1 :324
- 2 - B 15 OR2 3 1 0 1 :331
- 1 - B 15 OR2 3 1 0 1 :333
- 7 - B 15 OR2 3 1 1 1 :337
- 3 - B 15 OR2 3 1 0 1 :339
- 7 - C 09 OR2 3 1 0 1 :346
- 6 - C 09 OR2 3 1 0 1 :348
- 3 - C 09 OR2 3 1 1 1 :352
- 8 - C 09 OR2 3 1 0 1 :354
- 4 - C 09 OR2 3 1 0 1 :361
- 2 - C 09 OR2 3 1 0 1 :363
- 1 - C 09 OR2 3 1 1 1 :367
- 5 - C 09 OR2 3 1 0 1 :369
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\111\selling.rpt
selling
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 2/ 48( 4%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
B: 8/ 96( 8%) 0/ 48( 0%) 2/ 48( 4%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
C: 8/ 96( 8%) 3/ 48( 6%) 3/ 48( 6%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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