m60.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 632 行 · 第 1/2 页
RPT
632 行
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\111\m60.rpt
m60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: d:\111\m60.rpt
m60
** EQUATIONS **
clk : INPUT;
en : INPUT;
eq : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC1_A21;
-- Node name is 'c40'
-- Equation name is 'c40', type is output
c40 = GND;
-- Node name is 'c41'
-- Equation name is 'c41', type is output
c41 = VCC;
-- Node name is 'c42'
-- Equation name is 'c42', type is output
c42 = VCC;
-- Node name is 'c43'
-- Equation name is 'c43', type is output
c43 = VCC;
-- Node name is ':21' = 'dw0'
-- Equation name is 'dw0', location is LC1_A3, type is buried.
dw0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !en & eq
# !dw0 & eq & !_LC7_A23;
-- Node name is ':20' = 'dw1'
-- Equation name is 'dw1', location is LC5_A3, type is buried.
dw1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = dw0 & dw1 & _LC2_A3 & !_LC6_A3
# !dw0 & !dw1 & _LC2_A3 & !_LC6_A3;
-- Node name is ':19' = 'dw2'
-- Equation name is 'dw2', location is LC3_A3, type is buried.
dw2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = dw2 & _LC2_A3 & _LC4_A3 & !_LC6_A3
# !dw2 & _LC2_A3 & !_LC4_A3 & !_LC6_A3;
-- Node name is ':18' = 'dw3'
-- Equation name is 'dw3', location is LC7_A3, type is buried.
dw3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = eq & !_LC7_A23 & _LC8_A3
# !en & eq;
-- Node name is ':25' = 'gw0'
-- Equation name is 'gw0', location is LC3_A23, type is buried.
gw0 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = eq & _LC2_A18 & !_LC7_A23
# !en & eq;
-- Node name is ':24' = 'gw1'
-- Equation name is 'gw1', location is LC5_A23, type is buried.
gw1 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = gw0 & gw1 & _LC2_A23
# !gw0 & !gw1 & _LC2_A23 & _LC6_A3
# gw1 & _LC2_A23 & !_LC6_A3;
-- Node name is ':23' = 'gw2'
-- Equation name is 'gw2', location is LC8_A23, type is buried.
gw2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = eq & _LC6_A23 & !_LC7_A23
# !en & eq;
-- Node name is ':22' = 'gw3'
-- Equation name is 'gw3', location is LC4_A23, type is buried.
gw3 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = gw3 & _LC1_A23 & _LC2_A23
# !gw3 & !_LC1_A23 & _LC2_A23 & _LC6_A3
# gw3 & _LC2_A23 & !_LC6_A3;
-- Node name is 'h0'
-- Equation name is 'h0', type is output
h0 = gw0;
-- Node name is 'h1'
-- Equation name is 'h1', type is output
h1 = gw1;
-- Node name is 'h2'
-- Equation name is 'h2', type is output
h2 = gw2;
-- Node name is 'h3'
-- Equation name is 'h3', type is output
h3 = gw3;
-- Node name is 'l0'
-- Equation name is 'l0', type is output
l0 = dw0;
-- Node name is 'l1'
-- Equation name is 'l1', type is output
l1 = dw1;
-- Node name is 'l2'
-- Equation name is 'l2', type is output
l2 = dw2;
-- Node name is 'l3'
-- Equation name is 'l3', type is output
l3 = dw3;
-- Node name is '|LPM_ADD_SUB:85|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = LCELL( _EQ009);
_EQ009 = gw2
# gw1
# gw0;
-- Node name is '|LPM_ADD_SUB:90|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ010);
_EQ010 = dw1
# dw0;
-- Node name is ':4'
-- Equation name is '_LC1_A21', type is buried
_LC1_A21 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = eq & _LC1_A21
# !en & eq
# eq & _LC7_A23;
-- Node name is ':73'
-- Equation name is '_LC7_A23', type is buried
!_LC7_A23 = _LC7_A23~NOT;
_LC7_A23~NOT = LCELL( _EQ012);
_EQ012 = !_LC6_A3
# gw3
# _LC1_A23;
-- Node name is ':74'
-- Equation name is '_LC6_A3', type is buried
!_LC6_A3 = _LC6_A3~NOT;
_LC6_A3~NOT = LCELL( _EQ013);
_EQ013 = dw3
# dw2
# dw1
# dw0;
-- Node name is ':112'
-- Equation name is '_LC8_A3', type is buried
_LC8_A3 = LCELL( _EQ014);
_EQ014 = !dw0 & !dw1 & !dw2 & !dw3
# dw1 & dw3
# dw0 & dw3
# dw2 & dw3;
-- Node name is ':157'
-- Equation name is '_LC6_A23', type is buried
_LC6_A23 = LCELL( _EQ015);
_EQ015 = gw1 & gw2
# gw0 & gw2
# !gw0 & !gw1 & !gw2 & _LC6_A3
# gw2 & !_LC6_A3;
-- Node name is ':175'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = LCELL( _EQ016);
_EQ016 = gw0 & !_LC6_A3
# !gw0 & _LC6_A3;
-- Node name is '~269~1'
-- Equation name is '~269~1', location is LC2_A3, type is buried.
-- synthesized logic cell
_LC2_A3 = LCELL( _EQ017);
_EQ017 = en & eq;
-- Node name is '~287~1'
-- Equation name is '~287~1', location is LC2_A23, type is buried.
-- synthesized logic cell
_LC2_A23 = LCELL( _EQ018);
_EQ018 = en & eq & !_LC7_A23;
Project Information d:\111\m60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:03
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,700K
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