study10.rpt
来自「VHDL电子抢答器的实现。有多个文件」· RPT 代码 · 共 668 行 · 第 1/2 页
RPT
668 行
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Device-Specific Information: d:\111\study10.rpt
study10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: d:\111\study10.rpt
study10
** EQUATIONS **
clk : INPUT;
en : INPUT;
eq : INPUT;
-- Node name is 'alarm' from file "study10.tdf" line 24, column 15
-- Equation name is 'alarm', type is output
alarm = _LC3_A22;
-- Node name is 'h0' from file "study10.tdf" line 24, column 12
-- Equation name is 'h0', type is output
h0 = GND;
-- Node name is 'h1' from file "study10.tdf" line 24, column 12
-- Equation name is 'h1', type is output
h1 = GND;
-- Node name is 'h2' from file "study10.tdf" line 24, column 12
-- Equation name is 'h2', type is output
h2 = GND;
-- Node name is 'h3' from file "study10.tdf" line 24, column 12
-- Equation name is 'h3', type is output
h3 = GND;
-- Node name is 'l0~' from file "study10.tdf" line 7, column 23
-- Equation name is 'l0~', location is LC1_A16, type is buried.
l0~ = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC2_A16
# _LC2_A23
# _LC8_A20
# _LC1_A20;
-- Node name is 'l0' from file "study10.tdf" line 4, column 17
-- Equation name is 'l0', type is output
l0 = l0~;
-- Node name is 'l1~' from file "study10.tdf" line 7, column 23
-- Equation name is 'l1~', location is LC3_A16, type is buried.
l1~ = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC4_A16
# _LC6_A16
# _LC7_A22
# _LC2_A16;
-- Node name is 'l1' from file "study10.tdf" line 4, column 17
-- Equation name is 'l1', type is output
l1 = l1~;
-- Node name is 'l2~' from file "study10.tdf" line 7, column 23
-- Equation name is 'l2~', location is LC8_A16, type is buried.
l2~ = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC7_A16
# _LC4_A16
# _LC8_A20;
-- Node name is 'l2' from file "study10.tdf" line 4, column 17
-- Equation name is 'l2', type is output
l2 = l2~;
-- Node name is 'l3~' from file "study10.tdf" line 7, column 23
-- Equation name is 'l3~', location is LC5_A22, type is buried.
l3~ = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !en & s8
# !eq & s8
# s9;
-- Node name is 'l3' from file "study10.tdf" line 4, column 17
-- Equation name is 'l3', type is output
l3 = l3~;
-- Node name is 's1' from file "study10.tdf" line 10, column 3
-- Equation name is 's1', location is LC6_A20, type is buried.
s1 = LCELL( _EQ005);
_EQ005 = _LC2_A22 & !l3~;
-- Node name is 's4~1' from file "study10.tdf" line 13, column 3
-- Equation name is 's4~1', location is LC4_A20, type is buried.
-- synthesized logic cell
_LC4_A20 = LCELL( _EQ006);
_EQ006 = !l1~ & l2~;
-- Node name is 's4' from file "study10.tdf" line 13, column 3
-- Equation name is 's4', location is LC7_A20, type is buried.
s4 = LCELL( _EQ007);
_EQ007 = _LC4_A20 & !l0~ & !l3~;
-- Node name is 's5' from file "study10.tdf" line 14, column 3
-- Equation name is 's5', location is LC5_A20, type is buried.
s5 = LCELL( _EQ008);
_EQ008 = _LC4_A20 & l0~ & !l3~;
-- Node name is 's6~1' from file "study10.tdf" line 15, column 3
-- Equation name is 's6~1', location is LC3_A20, type is buried.
-- synthesized logic cell
_LC3_A20 = LCELL( _EQ009);
_EQ009 = !l0~ & l1~ & !l3~;
-- Node name is 's6' from file "study10.tdf" line 15, column 3
-- Equation name is 's6', location is LC2_A20, type is buried.
s6 = LCELL( _EQ010);
_EQ010 = _LC3_A20 & l2~;
-- Node name is 's7~1' from file "study10.tdf" line 16, column 3
-- Equation name is 's7~1', location is LC6_A22, type is buried.
-- synthesized logic cell
_LC6_A22 = LCELL( _EQ011);
_EQ011 = l0~ & l1~ & !l3~;
-- Node name is 's8' from file "study10.tdf" line 17, column 3
-- Equation name is 's8', location is LC4_A22, type is buried.
s8 = LCELL( _EQ012);
_EQ012 = !l0~ & !l1~ & !l2~ & l3~;
-- Node name is 's9~1' from file "study10.tdf" line 18, column 3
-- Equation name is 's9~1', location is LC2_A22, type is buried.
-- synthesized logic cell
_LC2_A22 = LCELL( _EQ013);
_EQ013 = l0~ & !l1~ & !l2~;
-- Node name is 's9' from file "study10.tdf" line 18, column 3
-- Equation name is 's9', location is LC8_A22, type is buried.
s9 = LCELL( _EQ014);
_EQ014 = _LC2_A22 & l3~;
-- Node name is '~39~5~1' from file "study10.tdf"
-- Equation name is '~39~5~1', location is LC8_A20, type is buried.
-- synthesized logic cell
_LC8_A20 = LCELL( _EQ015);
_EQ015 = _LC7_A22
# _LC1_A22 & s6
# !_LC1_A22 & s5;
-- Node name is '~39~5~2' from file "study10.tdf"
-- Equation name is '~39~5~2', location is LC1_A20, type is buried.
-- synthesized logic cell
_LC1_A20 = LCELL( _EQ016);
_EQ016 = _LC1_A22 & _LC3_A20 & !l2~
# !_LC1_A22 & s1;
-- Node name is '~40~4~1' from file "study10.tdf"
-- Equation name is '~40~4~1', location is LC6_A16, type is buried.
-- synthesized logic cell
_LC6_A16 = LCELL( _EQ017);
_EQ017 = _LC1_A23 & l1~ & !l2~
# _LC5_A16;
-- Node name is '~41~4~1' from file "study10.tdf"
-- Equation name is '~41~4~1', location is LC7_A16, type is buried.
-- synthesized logic cell
_LC7_A16 = LCELL( _EQ018);
_EQ018 = _LC1_A23 & _LC4_A20
# !_LC1_A22 & s4;
-- Node name is '~65~1' from file "study10.tdf" line 22, column 12
-- Equation name is '~65~1', location is LC1_A23, type is buried.
-- synthesized logic cell
_LC1_A23 = LCELL( _EQ019);
_EQ019 = _LC1_A22 & l0~ & !l3~;
-- Node name is '~65~2' from file "study10.tdf" line 22, column 12
-- Equation name is '~65~2', location is LC5_A16, type is buried.
-- synthesized logic cell
_LC5_A16 = LCELL( _EQ020);
_EQ020 = !_LC1_A22 & _LC3_A20 & !l2~;
-- Node name is ':65' from file "study10.tdf" line 22, column 12
-- Equation name is '_LC1_A22', type is buried
!_LC1_A22 = _LC1_A22~NOT;
_LC1_A22~NOT = LCELL( _EQ021);
_EQ021 = !en
# !eq;
-- Node name is ':105' from file "study10.tdf" line 33, column 7
-- Equation name is '_LC3_A22', type is buried
_LC3_A22 = LCELL( _EQ022);
_EQ022 = en & eq & _LC2_A22 & !l3~;
-- Node name is ':117' from file "study10.tdf" line 12, column 3
-- Equation name is '_LC2_A16', type is buried
_LC2_A16 = LCELL( _EQ023);
_EQ023 = _LC1_A22 & s4
# !_LC1_A22 & _LC6_A22 & !l2~;
-- Node name is ':123' from file "study10.tdf" line 15, column 3
-- Equation name is '_LC4_A16', type is buried
_LC4_A16 = LCELL( _EQ024);
_EQ024 = _LC1_A22 & _LC6_A22 & l2~
# !_LC1_A22 & _LC3_A20 & l2~;
-- Node name is ':125' from file "study10.tdf" line 16, column 3
-- Equation name is '_LC7_A22', type is buried
_LC7_A22 = LCELL( _EQ025);
_EQ025 = _LC1_A22 & s8
# !_LC1_A22 & _LC6_A22 & l2~;
-- Node name is ':128' from file "study10.tdf" line 18, column 3
-- Equation name is '_LC2_A23', type is buried
_LC2_A23 = LCELL( _EQ026);
_EQ026 = !_LC1_A22 & _LC2_A22 & l3~;
Project Information d:\111\study10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,696K
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