xianshi.vhd

来自「VHDL电子抢答器的实现。有多个文件」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
entity xianshi is
port(
		sel:in std_logic_vector(2 downto 0);
		d1,d2,d3,d4:in std_logic_vector(3 downto 0);
		q:out std_logic_vector(3 downto 0));
end xianshi;

architecture b of xianshi is
begin
	process(sel,d1,d2,d3,d4)
	begin
		case sel is
		when "000"=>q<=d1;
		when "001"=>q<=d2;
		when "111"=>q<=d3;
		when "110"=>q<=d4;
		when others=>q<="1111";
		end case;
	end process;
end b;