shift_split_data3.vhd

来自「关于一个串行数据输入 根据时序将数据分两路输出的程序」· VHDL 代码 · 共 84 行

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-- output is delayed 1 out of  4 circus, and 3 out of 4 circus.
-- output is not suitable for needed.
-- based on shift_split_data.vhd
-- make some changes
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity shift_split_data3 is
   port(iBitclk: in std_logic;
	     iFS1_clk: in std_logic;
		  iSSI_DIN: in std_logic;
		  iSSI_DIN_N: out std_logic_vector(1 downto 0));
end shift_split_data3;

architecture shift_split_data3_arch of shift_split_data3 is
    signal channel_counter1: std_logic_vector(5 downto 0) := "111111";
    signal iSSI_DIN_N_1: std_logic_vector(31 downto 0);
	 signal iSSI_DIN_N_2: std_logic_vector(63 downto 0);
	 signal iSSI_DIN_N_3: std_logic_vector(95 downto 0);
begin
    process(iFS1_clk,iBitclk)
	 begin

	    if(iBitclk'event and iBitclk='1') then
			 	 channel_counter1 <= channel_counter1 + 1;  				                     -- 32 is the highest value of channel_counter1
			 else 
			    channel_counter1 <= "111111";
		 end if;
    end process;

	 process(iBitclk,iFS1_clk,iSSI_DIN)
	 begin
	    if (rising_edge(iBitclk)) then
			    if(channel_counter1 < 32) then
		    	    iSSI_DIN_N(0) <= iSSI_DIN;
				 elsif(channel_counter1 > 32 and channel_counter1 < 63)
	 			    for i1 in 0 to 31 loop
                	  if (i1 = 0) then 
					    	 iSSI_DIN_N_1(0) <= iSSI_DIN;  
							         --iSSI_DIN_N_1 is the middle variable of the shift register data
                     else 
                      iSSI_DIN_N_1(i1) <= iSSI_DIN_N_1(i1-1);
                     end if;			  	
                end loop;
			       iSSI_DIN_N(0) <= iSSI_DIN_N_1(31);
			    end if;
		 end if;
	 end process;

    process(iBitclk,iFS1_clk,iSSI_DIN)
	 begin
	 	 if (rising_edge(iBitclk)) then
			    if(channel_counter1 < 32 )then
		    	    for i2 in 0 to 63 loop
                   if i2 = 0 then 
					       iSSI_DIN_N_2(0) <= iSSI_DIN;  
							         --iSSI_DIN_N_1 is the middle variable of the shift register data
                   else 
                      iSSI_DIN_N_2(i2) <= iSSI_DIN_N_2(i2-1);
                   end if;			  	
                end loop; 
			       iSSI_DIN_N(1) <= iSSI_DIN_N_2(63); 
             else
				    for i3 in 0 to 95 loop
                	 if i3 = 0 then 
					    	 iSSI_DIN_N_3(0) <= iSSI_DIN;  
							         --iSSI_DIN_N_1 is the middle variable of the shift register data
                   else 
                      iSSI_DIN_N_3(i3) <= iSSI_DIN_N_3(i3-1);
                   end if;
                end loop;
			       iSSI_DIN_N(1) <= iSSI_DIN_N_3(95);
				 end if;
			 end if;
	end process;
end shift_split_data3_arch;