moto.syr

使用CPLD进行驱动电机演示

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.30 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: moto.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "moto.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "moto"
Output Format                      : NGC
Target Device                      : XC9500 CPLDs

---- Source Options
Top Module Name                    : moto
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : moto.lso
verilog2001                        : YES
safe_implementation                : No
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/temp/Xilinx/moto/moto2/moto.vhd" in Library work.
Entity <moto> compiled.
Entity <moto> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <moto> (Architecture <behavioral>).
Entity <moto> analyzed. Unit <moto> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <moto>.
    Related source file is "D:/temp/Xilinx/moto/moto2/moto.vhd".
WARNING:Xst:1777 - Inout <CUTA<1>> is never used or assigned.
WARNING:Xst:1778 - Inout <CUTA<0>> is assigned but never used.
Unit <moto> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <moto> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : moto.ngr
Top Level Output File Name         : moto
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : XC9500 CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 2

Cell Usage :
# BELS                             : 1
#      GND                         : 1
# IO Buffers                       : 1
#      OBUF                        : 1
=========================================================================
CPU : 6.39 / 6.70 s | Elapsed : 6.00 / 6.00 s
 
--> 

Total memory usage is 90624 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)