📄 moto.rpt
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cpldfit: version I.24 Xilinx Inc.
Fitter Report
Design Name: moto Date: 3-26-2006, 11:50PM
Device Used: XC9536-10-VQ44
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
1 /36 ( 3%) 0 /180 ( 0%) 0 /72 ( 0%) 0 /36 ( 0%) 1 /34 ( 3%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 0/18 0/36 0 0/90 0/17
FB2 1/18 0/36 0 0/90 1/17
----- ----- ----- -----
1/36 0/72 0/180 1/34
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 0 0 | I/O : 0 28
Output : 1 1 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 1 1
** Power Data **
There are 1 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:1007 - Removing unused input(s) 'CUTA<1>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1006 - Design 'moto' has no inputs.
************************* Summary of Mapped Logic ************************
** 1 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
CUTA<0> 0 0 FB2_6 33 GSR/I/O O STD FAST
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 40 I/O
(unused) 0 0 0 5 FB1_2 41 I/O
(unused) 0 0 0 5 FB1_3 43 GCK/I/O
(unused) 0 0 0 5 FB1_4 42 I/O
(unused) 0 0 0 5 FB1_5 44 GCK/I/O
(unused) 0 0 0 5 FB1_6 2 I/O
(unused) 0 0 0 5 FB1_7 1 GCK/I/O
(unused) 0 0 0 5 FB1_8 3 I/O
(unused) 0 0 0 5 FB1_9 5 I/O
(unused) 0 0 0 5 FB1_10 6 I/O
(unused) 0 0 0 5 FB1_11 7 I/O
(unused) 0 0 0 5 FB1_12 8 I/O
(unused) 0 0 0 5 FB1_13 12 I/O
(unused) 0 0 0 5 FB1_14 13 I/O
(unused) 0 0 0 5 FB1_15 14 I/O
(unused) 0 0 0 5 FB1_16 16 I/O
(unused) 0 0 0 5 FB1_17 18 I/O
(unused) 0 0 0 5 FB1_18 (b)
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 39 I/O
(unused) 0 0 0 5 FB2_2 38 I/O
(unused) 0 0 0 5 FB2_3 36 GTS/I/O
(unused) 0 0 0 5 FB2_4 37 I/O
(unused) 0 0 0 5 FB2_5 34 GTS/I/O
CUTA<0> 0 0 0 5 FB2_6 33 GSR/I/O O
(unused) 0 0 0 5 FB2_7 32 I/O
(unused) 0 0 0 5 FB2_8 31 I/O
(unused) 0 0 0 5 FB2_9 30 I/O
(unused) 0 0 0 5 FB2_10 29 I/O
(unused) 0 0 0 5 FB2_11 28 I/O
(unused) 0 0 0 5 FB2_12 27 I/O
(unused) 0 0 0 5 FB2_13 23 I/O
(unused) 0 0 0 5 FB2_14 22 I/O
(unused) 0 0 0 5 FB2_15 21 I/O
(unused) 0 0 0 5 FB2_16 20 I/O
(unused) 0 0 0 5 FB2_17 19 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
CUTA<0> ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
CUTA(0) <= '0';
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9536-10-VQ44
--------------------------------
/44 43 42 41 40 39 38 37 36 35 34 \
| 1 33 |
| 2 32 |
| 3 31 |
| 4 30 |
| 5 XC9536-10-VQ44 29 |
| 6 28 |
| 7 27 |
| 8 26 |
| 9 25 |
| 10 24 |
| 11 23 |
\ 12 13 14 15 16 17 18 19 20 21 22 /
--------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TIE 23 TIE
2 TIE 24 TDO
3 TIE 25 GND
4 GND 26 VCC
5 TIE 27 TIE
6 TIE 28 TIE
7 TIE 29 TIE
8 TIE 30 TIE
9 TDI 31 TIE
10 TMS 32 TIE
11 TCK 33 CUTA<0>
12 TIE 34 TIE
13 TIE 35 VCC
14 TIE 36 TIE
15 VCC 37 TIE
16 TIE 38 TIE
17 GND 39 TIE
18 TIE 40 TIE
19 TIE 41 TIE
20 TIE 42 TIE
21 TIE 43 TIE
22 TIE 44 TIE
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9536-10-VQ44
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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