📄 statetrans3.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY statetrans3 IS
PORT(
Y : IN STD_LOGIC;
sel: OUT STD_LOGIC_vector(2 downto 0));
END statetrans3;
ARCHITECTURE a OF statetrans3 IS
ATTRIBUTE ENUM_ENCODING : string;
TYPE state IS(s0,s1,s2,s3);
ATTRIBUTE ENUM_ENCODING OF
State: TYPE is " 00 01 11 10";
SIGNAL ps : state;
SIGNAL ns : state;
BEGIN
PROCESS (Y)
BEGIN
IF Y'event and Y='1'THEN
ps<=ns;
END IF;
END PROCESS ;
PROCESS (ps)
BEGIN
CASE ps IS
WHEN s0 =>
ns<=s1;
sel(0)<='0'; --正常计时
sel(1)<='0';
sel(2)<='0';
WHEN s1=>
ns<=s2;
sel(0)<='0'; --调时
sel(1)<='0';
sel(2)<='1';
WHEN s2 =>
ns<=s3;
sel(0)<='0'; --调分
sel(1)<='1';
sel(2)<='0';
WHEN s3 =>
ns<=s0;
sel(0)<='1'; --调秒
sel(1)<='0';
sel(2)<='0';
END CASE;
END PROCESS ;
END a;
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