display.vhd

电子打铃器 在max plus 2 下编译通过

Library ieee;
USE IEEE.std_logic_1164.all;
Use IEEE.std_logic_arith.all;
Use IEEE.std_logic_unsigned.all;
entity display is
port(a,b,c,d,e,f:in std_logic_vector(3 downto 0); -- a b c d input data, con flash select
     con:in std_logic_vector(2 downto 0);
	 clk1,clk2  :in std_logic;                      -- clk1 scanning clock, clock2 flash clock
     sel        :out std_logic_vector(5 downto 0);
     q          :out std_logic_vector(7 downto 0));
end entity;

architecture dis of display IS

component convert                               --16 to 7
port(a:in std_logic_vector(3 downto 0);
	 sel2,sel4:in std_logic;
     b:out std_logic_vector(7 downto 0));
End component;

signal in1:std_logic_vector(3 downto 0);
signal temp,fil:std_logic_vector(2 downto 0);
signal tempsel:std_logic_vector(5 downto 0);
signal tempsel1,tempsel3:std_logic;


begin
	process(clk1)                            --scanning clock
	  begin
	 	if (clk1'event and clk1='1') then    -- generate the select signal
		        	if (temp= "000" ) then
		               	   temp<="101";
		        	else
		                   temp<=temp-'1';
		       	    end if;
		
		case temp is
			when"000"=>in1<=a;
			when"001"=>in1<=b;
			when"010"=>in1<=c;
			when"011"=>in1<=d;
			when"100"=>in1<=e;
			when"101"=>in1<=f;
			when others=>in1<="0000";
		end case;
		case temp is
			when"000"=>tempsel<="000001";
			when"001"=>tempsel<="000010";
			when"010"=>tempsel<="000100";
			when"011"=>tempsel<="001000";
			when"100"=>tempsel<="010000";
			when"101"=>tempsel<="100000";
			when others=>tempsel<="000000";
		end case;
     	end if;
	  end process;
		

		process(clk2)            -- generate the flash signal
			begin
				if con(0)='1' then
					sel(0)<=tempsel(0) and clk2;
					sel(1)<=tempsel(1) and clk2;
				else 
					sel(0)<=tempsel(0);
					sel(1)<=tempsel(1);
				end if;
				if con(1)='1' then
					sel(2)<=tempsel(2) and clk2;
					sel(3)<=tempsel(3) and clk2;
				else 
					sel(2)<=tempsel(2);
					sel(3)<=tempsel(3);
				end if;
				if con(2)='1' then
					sel(4)<=tempsel(4) and clk2;
					sel(5)<=tempsel(5) and clk2;
				else 
					sel(4)<=tempsel(4);
					sel(5)<=tempsel(5);
				end if;

		end process;
		tempsel1<=tempsel(1);tempsel3<=tempsel(3);

	U1:convert
	port map(in1,tempsel1,tempsel3,q);

	end dis;