clk_div.vhd

来自「电子打铃器 在max plus 2 下编译通过」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY CLK_DIV IS
	
	PORT(
		clk	: IN	STD_LOGIC;
		clk_div: OUT STD_LOGIC);
END CLK_DIV;

ARCHITECTURE a OF CLK_DIV IS
	SIGNAL count: STD_LOGIC_VECTOR(3 downto 0);

BEGIN
	
	PROCESS (clk)
	BEGIN
		IF clk'event and clk='1' THEN
			count<=count+1;
		END IF;
	END PROCESS ;
	clk_div<=count(3);
END a;