📄 scan.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY scan IS
PORT(
sel: IN STD_LOGIC_VECTOR(2 downto 0);
clk: IN STD_LOGIC;
I5,I4,I3,I2,I1,I0 : IN STD_LOGIC_VECTOR(3 downto 0);
Iout : OUT STD_LOGIC_VECTOR(7 downto 0);
L :BUFFER STD_LOGIC_VECTOR(5 downto 0));
end scan;
ARCHITECTURE a OF scan IS
SIGNAL count: STD_LOGIC_VECTOR(7 downto 0);
SIGNAL S : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL clk_div : STD_LOGIC;
BEGIN
PROCESS (clk)
BEGIN
IF clk'event and clk='1' THEN
count<=count+1;
else
null;
END IF;
END PROCESS;
clk_div<=count(7);
scanning:PROCESS (L)
BEGIN
IF L="000001" THEN
S<=I0;
END IF;
IF L="000010" THEN
S<=I1;
END IF;
IF L="000100" THEN
S<=I2;
END IF;
IF L="001000" THEN
S<=I3;
END IF;
IF L="010000" THEN
S<=I4;
END IF;
IF L="100000" THEN
S<=I5;
END IF;
IF L="000000" THEN
S<="0000";
END IF;
END PROCESS scanning;
PROCESS (clk,sel)
BEGIN
IF (clk'event and clk='1') THEN
IF sel="000" THEN
IF L="000000" THEN
L<="000001";
Iout(7)<='0';
END IF;
IF L="000001" THEN
L<="000010";
Iout(7)<='0';
END IF;
IF L="000010" THEN
L<="000100";
Iout(7)<='1';
END IF;
IF L="000100" THEN
L<="001000";
Iout(7)<='0';
END IF;
IF L="001000" THEN
L<="010000";
Iout(7)<='1';
END IF;
IF L="010000" THEN
L<="100000";
Iout(7)<='0';
END IF;
IF L="100000" THEN
L<="000001";
Iout(7)<='0';
END IF;
ELSIF sel="001" THEN
IF L="000000" THEN
IF clk_div='1' THEN
L<="000100";
Iout(7)<='1';
ELSE
L<="000001";
Iout(7)<='0';
END IF;
END IF;
IF L="000001" THEN
L<="000010";
Iout(7)<='0';
END IF;
IF L="000010" THEN
L<="000100";
Iout(7)<='1';
END IF;
IF L="000100" THEN
L<="001000";
Iout(7)<='0';
END IF;
IF L="001000" THEN
L<="010000";
Iout(7)<='1';
END IF;
IF L="010000" THEN
L<="100000";
Iout(7)<='0';
END IF;
IF L="100000" THEN
IF clk_div='1' THEN
L<="000100";
Iout(7)<='1';
ELSE
L<="000001";
Iout(7)<='0';
END IF;
END IF;
ELSIF sel="010" THEN
IF L="000000" THEN
L<="000001";
Iout(7)<='0';
END IF;
IF L="000001" THEN
L<="000010";
Iout(7)<='0';
END IF;
IF L="000010" THEN
IF clk_div='1' THEN
L<="010000";
Iout(7)<='1';
ELSE
L<="000100";
Iout(7)<='1';
END IF;
END IF;
IF L="000100" THEN
L<="001000";
Iout(7)<='0';
END IF;
IF L="001000" THEN
L<="010000";
Iout(7)<='1';
END IF;
IF L="010000" THEN
L<="100000";
Iout(7)<='0';
END IF;
IF L="100000" THEN
L<="000001";
Iout(7)<='0';
END IF;
ELSIF sel="100" THEN
IF L="000000" THEN
L<="000001";
Iout(7)<='0';
END IF;
IF L="000001" THEN
L<="000010";
Iout(7)<='0';
END IF;
IF L="000010" THEN
L<="000100";
Iout(7)<='1';
END IF;
IF L="000100" THEN
L<="001000";
Iout(7)<='0';
END IF;
IF L="001000" THEN
IF clk_div='1' THEN
L<="000001";
Iout(7)<='0';
ELSE
L<="010000";
Iout(7)<='1';
END IF;
END IF;
IF L="010000" THEN
L<="100000";
Iout(7)<='0';
END IF;
IF L="100000" THEN
L<="000001";
Iout(7)<='0';
END IF;
END IF;
END IF;
END PROCESS ;
decorder:PROCESS (S)
BEGIN
CASE S IS
WHEN "0000"=>
Iout(6 downto 0)<="1111110";
WHEN "0001" =>
Iout(6 downto 0)<="0110000";
WHEN "0010" =>
Iout(6 downto 0)<="1101101";
WHEN "0011" =>
Iout(6 downto 0)<="1111001";
WHEN "0100" =>
Iout(6 downto 0)<="0110011";
WHEN "0101" =>
Iout(6 downto 0)<="1011011";
WHEN "0110" =>
Iout(6 downto 0)<="1011111";
WHEN "0111" =>
Iout(6 downto 0)<="1110000";
WHEN "1000" =>
Iout(6 downto 0)<="1111111";
WHEN "1001" =>
Iout(6 downto 0)<="1111011";
WHEN OTHERS =>
Iout(6 downto 0)<="0000000";
END CASE;
END PROCESS decorder;
END a;
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