jishu_din.vhd

来自「电子打铃器 在max plus 2 下编译通过」· VHDL 代码 · 共 124 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY jishu_din IS
	
	PORT(
		CIN: IN	STD_LOGIC;
		sel: IN std_logic_vector(2 downto 0);
		p0,p1,p2,p3,p4,p5: OUT STD_LOGIC_VECTOR(3 downto 0)
		);
END jishu_din;

ARCHITECTURE a OF jishu_din IS
	SIGNAL q0,q1,q2,q3,q4,q5: STD_LOGIC_VECTOR(3 downto 0);
		
BEGIN
	
	PROCESS(CIN)
	BEGIN
			IF CIN'event and CIN='1' THEN
				IF  sel="010" THEN
					IF q2="1001" THEN
						q2<="0000";
					ELSE 
						q2<=q2+1;
					END IF;
				END IF;
			END IF;
	END PROCESS ;

	PROCESS (CIN)
	BEGIN
			IF CIN'event and CIN='1' THEN
				IF sel="010" THEN
					IF q2="1001" THEN
						IF q3="0101" THEN
							q3<="0000";
						ELSE 
							q3<=q3+1;
						END IF;
					END IF;
				END IF;

			END IF;

	END PROCESS ;
	PROCESS (CIN)
	BEGIN
		IF CIN'event and CIN='1' THEN
			IF sel="100" THEN
				IF q4="1001" THEN
					q4<="0000";
								
				ELSIF q4="0011" and q5="0010" THEN
					q4<="0000";
				ELSE
					q4<=q4+1;

				END IF;

					
			END IF;
		END IF;
	END PROCESS ;
	
	PROCESS (CIN)
	BEGIN
		IF CIN'event and CIN='1' THEN
			IF  sel="100" THEN
				IF q4="1001" THEN
					q5<=q5+1;
				
				ELSIF q4="0011" and q5="0010" THEN
					q5<="0000";	
					
				END IF;
			END IF;
		END IF;
	END PROCESS ;

	PROCESS(CIN)
	BEGIN
			IF CIN'event and CIN='1' THEN
				IF  sel="001" THEN
					IF q0="1001" THEN
						q0<="0000";
					ELSE 
						q0<=q0+1;
					END IF;
				END IF;
			END IF;
	END PROCESS ;

	PROCESS (CIN)
	BEGIN
			IF CIN'event and CIN='1' THEN
				IF sel="001" THEN
					IF q0="1001" THEN
						IF q1="0101" THEN
							q1<="0000";
						ELSE 
							q1<=q1+1;
						END IF;
					END IF;
				END IF;

			END IF;

	END PROCESS;	

	p1<=q1;
	p0<=q0;
	p2<=q2;
	p3<=q3;
	p4<=q4;
	p5<=q5;
END a;