minusone.vhd

电子打铃器 在max plus 2 下编译通过

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity minusone is
port(
	q1,q2,q3,q4:in std_logic_vector(3 downto 0);
	data1,data2,data3,data4:out std_logic_vector(3 downto 0)
	);
end minusone;

architecture rtl of minusone is
begin
	data1<=q1-1;
	data2<=q2;
	data3<=q3-1;
	data4<=q4;
end rtl;