📄 displaysel.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY displaysel IS
PORT(
jishusel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
selectcon: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END displaysel;
ARCHITECTURE a OF displaysel IS
BEGIN
PROCESS (jishusel)
BEGIN
IF jishusel(0)='1'THEN
selectcon<="100";
ELSIF jishusel(1)='1' THEN
selectcon<="010";
ELSIF jishusel(2)='1' THEN
selectcon<="001";
ELSE
selectcon<="000";
END IF;
END PROCESS ;
END a;
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