a6850.fit.eqn

本文件是altera公司fpga的ip核

--S1L01 is stsrg:u4|rx_stsrg:u2|local_data_done~72 at LC_X20_Y6_N0
--operation mode is normal

S1L01 = S1_int_dout[4] & S1_sts_done;


--H1_sts_reg1_re is bus_cntl:u7|sts_reg1_re at LC_X20_Y6_N5
--operation mode is normal

H1_sts_reg1_re_lut_out = rw_n & H1L12 & !rs;
H1_sts_reg1_re = DFFEAS(H1_sts_reg1_re_lut_out, !GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--S1L61 is stsrg:u4|rx_stsrg:u2|local_sts_done~67 at LC_X20_Y6_N2
--operation mode is normal

H1_sts_reg2_re_qfbk = H1_sts_reg2_re;
S1L61 = H1_sts_reg2_re_qfbk & !H1_sts_reg1_re;

--H1_sts_reg2_re is bus_cntl:u7|sts_reg2_re at LC_X20_Y6_N2
--operation mode is normal

H1_sts_reg2_re = DFFEAS(S1L61, GLOBAL(rxclk), GLOBAL(reset), , , H1_sts_reg1_re, , , VCC);


--H1_dataq[7] is bus_cntl:u7|dataq[7] at LC_X15_Y9_N2
--operation mode is normal

H1_dataq[7]_lut_out = di[7];
H1_dataq[7] = DFFEAS(H1_dataq[7]_lut_out, GLOBAL(txclk), GLOBAL(reset), , e, , , , );


--U1L1 is tcntl:u8|datacnt:u2|add~286 at LC_X16_Y9_N5
--operation mode is normal

U1L1 = U1_int_dout[0] & T1_state.data & T1L2 & !V1L3;


--T1L1 is tcntl:u8|transm:u1|clr_datacnt~47 at LC_X17_Y9_N2
--operation mode is normal

T1L1 = U1L6 & !G1L01 & T1_state.data & !V1L3;


--L1L5 is xmit_reg:u10|int_dout[2]~51 at LC_X16_Y7_N9
--operation mode is normal

L1L5 = H1_tx_reg2_we & (G1_int_dout[0] & G1_int_dout[1] # !H1_tx_reg1_we) # !H1_tx_reg2_we & G1_int_dout[0] & G1_int_dout[1];


--Y1_data_int[2] is srpargen:u9|tshftrg:u3|data_int[2] at LC_X15_Y7_N0
--operation mode is normal

Y1_data_int[2]_lut_out = !G1L01 & (T1L9 & (L1_int_dout[2]) # !T1L9 & Y1_data_int[3]);
Y1_data_int[2] = DFFEAS(Y1_data_int[2]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , Y1L4, , , , );


--M1L01 is rxcntl:u1|rxcntlsm:u1|next_state.db1_data~107 at LC_X19_Y9_N1
--operation mode is normal

M1L01 = !G1_int_dout[0] & !rxdata & !G1_int_dout[1] & !M1_state.wait_start;


--M1_state.wait_data is rxcntl:u1|rxcntlsm:u1|state.wait_data at LC_X17_Y6_N0
--operation mode is normal

M1_state.wait_data_lut_out = M1L41 # M1L51 # !G1L01 & M1L31;
M1_state.wait_data = DFFEAS(M1_state.wait_data_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--M1L42 is rxcntl:u1|rxcntlsm:u1|Select~447 at LC_X18_Y6_N9
--operation mode is normal

M1L42 = M1L6 & (M1_state.wait_data & P1L32);

--M1_state.sample_data is rxcntl:u1|rxcntlsm:u1|state.sample_data at LC_X18_Y6_N9
--operation mode is normal

M1_state.sample_data = DFFEAS(M1L42, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--M1_state.wait_parity is rxcntl:u1|rxcntlsm:u1|state.wait_parity at LC_X18_Y7_N9
--operation mode is normal

M1_state.wait_parity_lut_out = !G1L01 & (M1L61 # !P1L32 & M1_state.wait_parity);
M1_state.wait_parity = DFFEAS(M1_state.wait_parity_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--M1L52 is rxcntl:u1|rxcntlsm:u1|Select~448 at LC_X17_Y6_N8
--operation mode is normal

M1L52 = M1_state.wait_parity & (M1L6 & P1L32);

--M1_state.sample_parity is rxcntl:u1|rxcntlsm:u1|state.sample_parity at LC_X17_Y6_N8
--operation mode is normal

M1_state.sample_parity = DFFEAS(M1L52, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--M1L7 is rxcntl:u1|rxcntlsm:u1|dat_clr~145 at LC_X19_Y10_N8
--operation mode is normal

M1L7 = !M1_state.db1_data & (!M1_state.sample_data);


--M1L8 is rxcntl:u1|rxcntlsm:u1|dat_clr~146 at LC_X18_Y10_N5
--operation mode is normal

M1L8 = !G1L01 & (N1L31 & !M1L7 # !M1_state.wait_start);


--M1L62 is rxcntl:u1|rxcntlsm:u1|shift_en~12 at LC_X19_Y10_N9
--operation mode is normal

M1L62 = G1L01 # !M1_state.sample_data & !M1_state.sample_parity & M1L4;


--M1L81 is rxcntl:u1|rxcntlsm:u1|next_state.wait_stop1~161 at LC_X17_Y6_N3
--operation mode is normal

M1L81 = M1_state.wait_stop1 & (!M1L6 # !P1L32);


--M1L91 is rxcntl:u1|rxcntlsm:u1|next_state.wait_stop1~162 at LC_X18_Y10_N9
--operation mode is normal

M1L91 = M1_state.sample_data & !G1L11 & N1L31 & !M1L62;


--M1_state.synch is rxcntl:u1|rxcntlsm:u1|state.synch at LC_X19_Y9_N7
--operation mode is normal

M1_state.synch_lut_out = !rxdata & M1L21 & (!G1_int_dout[1] # !G1_int_dout[0]);
M1_state.synch = DFFEAS(M1_state.synch_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--P1L91 is rxcntl:u1|rxcount:u3|int_tc1~124 at LC_X19_Y6_N5
--operation mode is normal

P1L91 = P1_int_dout[4] & P1_int_dout[3] & (G1_int_dout[1] # !G1_int_dout[0]) # !P1_int_dout[4] & G1_int_dout[0] & !G1_int_dout[1] & !P1_int_dout[3];


--P1L02 is rxcntl:u1|rxcount:u3|int_tc1~125 at LC_X19_Y6_N3
--operation mode is normal

P1L02 = !P1_int_dout[5] & (P1L22 & P1L91);


--M1L31 is rxcntl:u1|rxcntlsm:u1|next_state.wait_data~98 at LC_X19_Y6_N4
--operation mode is normal

M1L31 = !rxdata & M1_state.synch & M1L6 & P1L02;


--M1L1 is rxcntl:u1|rxcntlsm:u1|clr_cnt~175 at LC_X18_Y6_N7
--operation mode is normal

M1L1 = M1L42 # M1L31 # M1L52 # !M1_state.wait_start;


--M1L2 is rxcntl:u1|rxcntlsm:u1|clr_cnt~176 at LC_X18_Y6_N8
--operation mode is normal

M1L2 = !G1L01 & (M1L12 # M1L22 # M1L1);


--M1L02 is rxcntl:u1|rxcntlsm:u1|next_state.wait_stop2~203 at LC_X19_Y7_N4
--operation mode is normal

M1L02 = !G1_int_dout[3] & M1_state.sample_stop1 & (!G1_int_dout[2] # !G1_int_dout[4]);


--Y1_data_int[3] is srpargen:u9|tshftrg:u3|data_int[3] at LC_X15_Y7_N1
--operation mode is normal

Y1_data_int[3]_lut_out = !G1L01 & (T1L9 & (L1_int_dout[3]) # !T1L9 & Y1_data_int[4]);
Y1_data_int[3] = DFFEAS(Y1_data_int[3]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , Y1L4, , , , );


--M1L41 is rxcntl:u1|rxcntlsm:u1|next_state.wait_data~99 at LC_X17_Y6_N9
--operation mode is normal

M1L41 = !G1L01 & M1_state.wait_data & (!M1L6 # !P1L32);


--M1L51 is rxcntl:u1|rxcntlsm:u1|next_state.wait_data~100 at LC_X18_Y10_N8
--operation mode is normal

M1L51 = M1_state.sample_data & !G1L01 & (M1L62 # !N1L31);


--M1L61 is rxcntl:u1|rxcntlsm:u1|next_state.wait_parity~219 at LC_X18_Y7_N8
--operation mode is normal

M1L61 = M1_state.sample_data & G1L11 & !G1L01 & N1L31;


--M1L21 is rxcntl:u1|rxcntlsm:u1|next_state.synch~205 at LC_X19_Y9_N6
--operation mode is normal

M1L21 = M1_state.wait_start & (M1_state.synch & !P1L02) # !M1_state.wait_start & (M1_state.synch & !P1L02 # !M1L9);


--Y1_data_int[4] is srpargen:u9|tshftrg:u3|data_int[4] at LC_X15_Y7_N7
--operation mode is normal

Y1_data_int[4]_lut_out = !G1L01 & (T1L9 & L1_int_dout[4] # !T1L9 & (Y1_data_int[5]));
Y1_data_int[4] = DFFEAS(Y1_data_int[4]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , Y1L4, , , , );


--Y1_data_int[5] is srpargen:u9|tshftrg:u3|data_int[5] at LC_X15_Y7_N8
--operation mode is normal

Y1_data_int[5]_lut_out = !G1L01 & (T1L9 & (L1_int_dout[5]) # !T1L9 & Y1_data_int[6]);
Y1_data_int[5] = DFFEAS(Y1_data_int[5]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , Y1L4, , , , );


--Y1_data_int[6] is srpargen:u9|tshftrg:u3|data_int[6] at LC_X15_Y7_N2
--operation mode is normal

Y1_data_int[6]_lut_out = !G1L01 & (T1L9 & L1_int_dout[6] # !T1L9 & (Y1_data_int[7]));
Y1_data_int[6] = DFFEAS(Y1_data_int[6]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , Y1L4, , , , );


--Y1_data_int[7] is srpargen:u9|tshftrg:u3|data_int[7] at LC_X17_Y7_N8
--operation mode is normal

Y1_data_int[7]_lut_out = Y1_data_int[7] & (W1L1 & T1L3 # !Y1L4) # !Y1_data_int[7] & W1L1 & (T1L3);
Y1_data_int[7] = DFFEAS(Y1_data_int[7]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--S1L41 is stsrg:u4|rx_stsrg:u2|local_ovr~146 at LC_X19_Y8_N6
--operation mode is normal

S1L41 = M1L32 # G1_int_dout[1] & G1_int_dout[0];


--rs is rs at PIN_41
--operation mode is input

rs = INPUT();


--rxclk is rxclk at PIN_66
--operation mode is input

rxclk = INPUT();


--reset is reset at PIN_34
--operation mode is input

reset = INPUT();


--cts is cts at PIN_38
--operation mode is input

cts = INPUT();


--txclk is txclk at PIN_10
--operation mode is input

txclk = INPUT();


--dcd is dcd at PIN_42
--operation mode is input

dcd = INPUT();


--rxdata is rxdata at PIN_84
--operation mode is input

rxdata = INPUT();


--rw_n is rw_n at PIN_40
--operation mode is input

rw_n = INPUT();


--cs[2] is cs[2] at PIN_71
--operation mode is input

cs[2] = INPUT();


--cs[1] is cs[1] at PIN_72
--operation mode is input

cs[1] = INPUT();


--e is e at PIN_77
--operation mode is input

e = INPUT();


--cs[0] is cs[0] at PIN_73
--operation mode is input

cs[0] = INPUT();


--di[6] is di[6] at PIN_37
--operation mode is input

di[6] = INPUT();


--di[5] is di[5] at PIN_36
--operation mode is input

di[5] = INPUT();


--di[1] is di[1] at PIN_88
--operation mode is input

di[1] = INPUT();


--di[0] is di[0] at PIN_85
--operation mode is input

di[0] = INPUT();


--di[3] is di[3] at PIN_87
--operation mode is input

di[3] = INPUT();


--di[4] is di[4] at PIN_92
--operation mode is input

di[4] = INPUT();


--di[2] is di[2] at PIN_90
--operation mode is input

di[2] = INPUT();


--di[7] is di[7] at PIN_89
--operation mode is input

di[7] = INPUT();


--do[0] is do[0] at PIN_79
--operation mode is output

do[0] = OUTPUT(H1L31);


--do[1] is do[1] at PIN_86
--operation mode is output

do[1] = OUTPUT(H1L41);


--do[2] is do[2] at PIN_56
--operation mode is output

do[2] = OUTPUT(H1L51);


--do[3] is do[3] at PIN_68
--operation mode is output

do[3] = OUTPUT(H1L61);


--do[4] is do[4] at PIN_65
--operation mode is output

do[4] = OUTPUT(H1L71);


--do[5] is do[5] at PIN_47
--operation mode is output

do[5] = OUTPUT(H1L81);


--do[6] is do[6] at PIN_57
--operation mode is output

do[6] = OUTPUT(H1L91);


--do[7] is do[7] at PIN_48
--operation mode is output

do[7] = OUTPUT(H1L02);


--irq_n is irq_n at PIN_69
--operation mode is output

irq_n = OUTPUT(!E1_sts_reg[7]);


--txdata is txdata at PIN_70
--operation mode is output

txdata = OUTPUT(AB1L3);


--rts is rts at PIN_39
--operation mode is output

rts = OUTPUT(G1L31);