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📄 a6850.fit.eqn

📁 本文件是altera公司fpga的ip核
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--D1_int_dout[0] is rcv_reg:u3|int_dout[0] at LC_X18_Y8_N3
--operation mode is normal

D1_int_dout[0]_lut_out = F1L21 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[0] = DFFEAS(D1_int_dout[0]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--H1L31 is bus_cntl:u7|do[0]~102 at LC_X18_Y8_N8
--operation mode is normal

H1L31 = rs & (D1_int_dout[0]) # !rs & S1_int_dout[5];


--D1_int_dout[1] is rcv_reg:u3|int_dout[1] at LC_X18_Y8_N6
--operation mode is normal

D1_int_dout[1]_lut_out = F1L31 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[1] = DFFEAS(D1_int_dout[1]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--R1_int_dout[2] is stsrg:u4|tx_stsrg:u1|int_dout[2] at LC_X16_Y7_N2
--operation mode is normal

R1_int_dout[2]_lut_out = !R1L7;
R1_int_dout[2] = DFFEAS(R1_int_dout[2]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--H1L41 is bus_cntl:u7|do[1]~103 at LC_X18_Y9_N4
--operation mode is normal

H1L41 = rs & D1_int_dout[1] # !rs & (!R1_int_dout[2]);


--D1_int_dout[2] is rcv_reg:u3|int_dout[2] at LC_X20_Y8_N2
--operation mode is normal

D1_int_dout[2]_lut_out = F1L41 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[2] = DFFEAS(D1_int_dout[2]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--H1L51 is bus_cntl:u7|do[2]~104 at LC_X20_Y6_N1
--operation mode is normal

H1L51 = rs & (D1_int_dout[2]) # !rs & (S1_int_dout[4]);


--D1_int_dout[3] is rcv_reg:u3|int_dout[3] at LC_X20_Y8_N3
--operation mode is normal

D1_int_dout[3]_lut_out = F1L51 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[3] = DFFEAS(D1_int_dout[3]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--H1L61 is bus_cntl:u7|do[3]~105 at LC_X20_Y8_N7
--operation mode is normal

H1L61 = rs & (D1_int_dout[3]) # !rs & (R1_int_dout[1]);


--D1_int_dout[4] is rcv_reg:u3|int_dout[4] at LC_X20_Y8_N6
--operation mode is normal

D1_int_dout[4]_lut_out = F1L61 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[4] = DFFEAS(D1_int_dout[4]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--S1_int_dout[3] is stsrg:u4|rx_stsrg:u2|int_dout[3] at LC_X20_Y8_N0
--operation mode is normal

S1_int_dout[3]_lut_out = A1L03 & (!G1_int_dout[1] # !G1_int_dout[0]);
S1_int_dout[3] = DFFEAS(S1_int_dout[3]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--H1L71 is bus_cntl:u7|do[4]~106 at LC_X20_Y8_N9
--operation mode is normal

H1L71 = rs & (D1_int_dout[4]) # !rs & S1_int_dout[3];


--D1_int_dout[5] is rcv_reg:u3|int_dout[5] at LC_X20_Y8_N8
--operation mode is normal

D1_int_dout[5]_lut_out = F1L71 & (!G1_int_dout[1] # !G1_int_dout[0]);
D1_int_dout[5] = DFFEAS(D1_int_dout[5]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--H1L81 is bus_cntl:u7|do[5]~107 at LC_X19_Y8_N9
--operation mode is normal

H1L81 = rs & (D1_int_dout[5]) # !rs & S1_int_dout[2];


--D1_int_dout[6] is rcv_reg:u3|int_dout[6] at LC_X18_Y8_N5
--operation mode is normal

D1_int_dout[6]_lut_out = F1L81 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[6] = DFFEAS(D1_int_dout[6]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--S1_int_dout[1] is stsrg:u4|rx_stsrg:u2|int_dout[1] at LC_X18_Y8_N2
--operation mode is normal

S1_int_dout[1]_lut_out = G1L11 & !G1L01 & (C1L1 $ C1L3);
S1_int_dout[1] = DFFEAS(S1_int_dout[1]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--H1L91 is bus_cntl:u7|do[6]~108 at LC_X20_Y8_N5
--operation mode is normal

H1L91 = rs & (D1_int_dout[6]) # !rs & S1_int_dout[1];


--D1_int_dout[7] is rcv_reg:u3|int_dout[7] at LC_X18_Y8_N4
--operation mode is normal

D1_int_dout[7]_lut_out = F1L91 & (!G1_int_dout[0] # !G1_int_dout[1]);
D1_int_dout[7] = DFFEAS(D1_int_dout[7]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , S1L41, , , , );


--S1_int_dout[0] is stsrg:u4|rx_stsrg:u2|int_dout[0] at LC_X19_Y8_N3
--operation mode is normal

S1_int_dout[0]_lut_out = G1_int_dout[7] & (S1L21 # S1L31 # S1L51);
S1_int_dout[0] = DFFEAS(S1_int_dout[0]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--R1_int_dout[0] is stsrg:u4|tx_stsrg:u1|int_dout[0] at LC_X16_Y7_N4
--operation mode is normal

R1_int_dout[0]_lut_out = G1_int_dout[5] & (!G1_int_dout[6] & R1L7);
R1_int_dout[0] = DFFEAS(R1_int_dout[0]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--H1L02 is bus_cntl:u7|do[7]~109 at LC_X20_Y8_N1
--operation mode is normal

H1L02 = rs & (D1_int_dout[7]) # !rs & (R1_int_dout[0] # S1_int_dout[0]);


--E1_sts_reg[7] is stsrg:u4|sts_reg[7] at LC_X20_Y8_N4
--operation mode is normal

E1_sts_reg[7] = S1_int_dout[0] # R1_int_dout[0];


--G1L01 is cntl_reg:u6|mr~0 at LC_X18_Y8_N7
--operation mode is normal

G1L01 = G1_int_dout[1] & G1_int_dout[0];


--T1_state.parity is tcntl:u8|transm:u1|state.parity at LC_X17_Y9_N8
--operation mode is normal

T1_state.parity_lut_out = G1L11 & !G1L01 & U1L6 & T1_state.data;
T1_state.parity = DFFEAS(T1_state.parity_lut_out, !GLOBAL(txclk), GLOBAL(reset), , T1L7, , , , );


--X1_parity is srpargen:u9|pargen:u2|parity at LC_X17_Y7_N2
--operation mode is normal

X1_parity_lut_out = W1L1 $ X1L2 $ (G1L11 & G1_int_dout[2]);
X1_parity = DFFEAS(X1_parity_lut_out, !GLOBAL(txclk), GLOBAL(reset), , T1L3, , , , );


--T1_state.data is tcntl:u8|transm:u1|state.data at LC_X17_Y7_N4
--operation mode is normal

T1_state.data_lut_out = T1L4 # !G1L01 & T1_state.start & !V1L3;
T1_state.data = DFFEAS(T1_state.data_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--T1_state.start is tcntl:u8|transm:u1|state.start at LC_X17_Y7_N9
--operation mode is normal

T1_state.start_lut_out = T1L3 # !G1L01 & T1_state.start & !V1_tc;
T1_state.start = DFFEAS(T1_state.start_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--Y1_data_int[0] is srpargen:u9|tshftrg:u3|data_int[0] at LC_X15_Y7_N4
--operation mode is normal

Y1_data_int[0]_lut_out = !G1L01 & (T1L9 & L1_int_dout[0] # !T1L9 & (Y1_data_int[1]));
Y1_data_int[0] = DFFEAS(Y1_data_int[0]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , Y1L4, , , , );


--AB1L1 is srpargen:u9|brkmux:u5|txdata~256 at LC_X17_Y9_N5
--operation mode is normal

AB1L1 = T1_state.start & (!T1_state.data # !X1_parity) # !T1_state.start & !Y1_data_int[0] & (T1_state.data);


--AB1L2 is srpargen:u9|brkmux:u5|txdata~257 at LC_X17_Y9_N6
--operation mode is normal

AB1L2 = T1_state.parity & !X1_parity # !T1_state.parity & (AB1L1);


--AB1L3 is srpargen:u9|brkmux:u5|txdata~258 at LC_X17_Y8_N6
--operation mode is normal

G1_int_dout[6]_qfbk = G1_int_dout[6];
AB1L3 = G1L01 & (!G1_int_dout[5] # !G1_int_dout[6]_qfbk) # !G1L01 & !AB1L2 & (!G1_int_dout[5] # !G1_int_dout[6]_qfbk);

--G1_int_dout[6] is cntl_reg:u6|int_dout[6] at LC_X17_Y8_N6
--operation mode is normal

G1_int_dout[6] = DFFEAS(AB1L3, !GLOBAL(txclk), GLOBAL(reset), , H1_cntl_we, H1_dataq[6], , , VCC);


--G1L31 is cntl_reg:u6|tx_irq_en~27 at LC_X17_Y8_N2
--operation mode is normal

G1_int_dout[5]_qfbk = G1_int_dout[5];
G1L31 = !G1_int_dout[5]_qfbk & G1_int_dout[6];

--G1_int_dout[5] is cntl_reg:u6|int_dout[5] at LC_X17_Y8_N2
--operation mode is normal

G1_int_dout[5] = DFFEAS(G1L31, !GLOBAL(txclk), GLOBAL(reset), , H1_cntl_we, H1_dataq[5], , , VCC);


--F1_data[0] is rxshftrg:u5|data[0] at LC_X19_Y10_N7
--operation mode is normal

F1_data[0]_lut_out = F1_data[1] & (!G1_int_dout[1] # !G1_int_dout[0]);
F1_data[0] = DFFEAS(F1_data[0]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , F1L6, , , , );


--F1_data[1] is rxshftrg:u5|data[1] at LC_X19_Y10_N5
--operation mode is normal

F1_data[1]_lut_out = F1_data[2] & (!G1_int_dout[1] # !G1_int_dout[0]);
F1_data[1] = DFFEAS(F1_data[1]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , F1L6, , , , );


--F1L21 is rxshftrg:u5|par_out[0]~657 at LC_X19_Y10_N2
--operation mode is normal

F1L21 = G1_int_dout[3] & (G1_int_dout[4] & F1_data[0] # !G1_int_dout[4] & (F1_data[1])) # !G1_int_dout[3] & (F1_data[1]);


--M1_state.db1_stop1 is rxcntl:u1|rxcntlsm:u1|state.db1_stop1 at LC_X20_Y6_N7
--operation mode is normal

M1_state.db1_stop1_lut_out = !G1L01 & (M1_state.db1_parity # N1L31 & M1L11);
M1_state.db1_stop1 = DFFEAS(M1_state.db1_stop1_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--A1L92 is rtl~371 at LC_X20_Y6_N6
--operation mode is normal

A1L92 = M1_state.db1_stop1 # M1_state.sample_stop1;


--G1L21 is cntl_reg:u6|stop_bits~36 at LC_X17_Y8_N3
--operation mode is normal

G1_int_dout[4]_qfbk = G1_int_dout[4];
G1L21 = !G1_int_dout[3] & (!G1_int_dout[2] # !G1_int_dout[4]_qfbk);

--G1_int_dout[4] is cntl_reg:u6|int_dout[4] at LC_X17_Y8_N3
--operation mode is normal

G1_int_dout[4] = DFFEAS(G1L21, !GLOBAL(txclk), GLOBAL(reset), , H1_cntl_we, H1_dataq[4], , , VCC);


--M1_state.overrun is rxcntl:u1|rxcntlsm:u1|state.overrun at LC_X19_Y6_N8
--operation mode is normal

M1_state.overrun_lut_out = S1_int_dout[5] & M1L71 & (!G1_int_dout[1] # !G1_int_dout[0]);
M1_state.overrun = DFFEAS(M1_state.overrun_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--M1_state.db1_stop2 is rxcntl:u1|rxcntlsm:u1|state.db1_stop2 at LC_X19_Y6_N0
--operation mode is normal

M1_state.db1_stop2_lut_out = G1L21 & M1_state.db1_stop1 & (!G1_int_dout[0] # !G1_int_dout[1]);
M1_state.db1_stop2 = DFFEAS(M1_state.db1_stop2_lut_out, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--M1L3 is rxcntl:u1|rxcntlsm:u1|cnt_en~70 at LC_X19_Y6_N7
--operation mode is normal

M1_state.sample_stop2_qfbk = M1_state.sample_stop2;
M1L3 = !M1_state.overrun & !M1_state.sample_stop2_qfbk & !M1_state.db1_stop2;

--M1_state.sample_stop2 is rxcntl:u1|rxcntlsm:u1|state.sample_stop2 at LC_X19_Y6_N7
--operation mode is normal

M1_state.sample_stop2 = DFFEAS(M1L3, GLOBAL(rxclk), GLOBAL(reset), , , M1L22, , , VCC);


--M1L32 is rxcntl:u1|rxcntlsm:u1|Select~446 at LC_X19_Y8_N5
--operation mode is normal

M1L32 = !S1_int_dout[5] & (!G1L21 & A1L92 # !M1L3);


--H1_rx_reg1_re is bus_cntl:u7|rx_reg1_re at LC_X19_Y8_N0
--operation mode is normal

H1_rx_reg1_re_lut_out = rs & (rw_n & H1L12);
H1_rx_reg1_re = DFFEAS(H1_rx_reg1_re_lut_out, !GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--S1L9 is stsrg:u4|rx_stsrg:u2|local_data_done~71 at LC_X19_Y8_N1
--operation mode is normal

H1_rx_reg2_re_qfbk = H1_rx_reg2_re;
S1L9 = H1_rx_reg2_re_qfbk & !H1_rx_reg1_re;

--H1_rx_reg2_re is bus_cntl:u7|rx_reg2_re at LC_X19_Y8_N1
--operation mode is normal

H1_rx_reg2_re = DFFEAS(S1L9, GLOBAL(rxclk), GLOBAL(reset), , , H1_rx_reg1_re, , , VCC);


--S1L51 is stsrg:u4|rx_stsrg:u2|local_rdrf~68 at LC_X19_Y8_N2
--operation mode is normal

S1_int_dout[5]_qfbk = S1_int_dout[5];
S1L51 = !G1L01 & !S1L9 & (M1L32 # S1_int_dout[5]_qfbk);

--S1_int_dout[5] is stsrg:u4|rx_stsrg:u2|int_dout[5] at LC_X19_Y8_N2
--operation mode is normal

S1_int_dout[5] = DFFEAS(S1L51, GLOBAL(rxclk), GLOBAL(reset), , , , , , );


--F1_data[2] is rxshftrg:u5|data[2] at LC_X19_Y10_N3
--operation mode is normal

F1_data[2]_lut_out = F1_data[3] & (!G1_int_dout[1] # !G1_int_dout[0]);
F1_data[2] = DFFEAS(F1_data[2]_lut_out, GLOBAL(rxclk), GLOBAL(reset), , F1L6, , , , );


--F1L31 is rxshftrg:u5|par_out[1]~658 at LC_X19_Y10_N6
--operation mode is normal

F1L31 = G1_int_dout[3] & (G1_int_dout[4] & (F1_data[1]) # !G1_int_dout[4] & F1_data[2]) # !G1_int_dout[3] & F1_data[2];


--H1_tx_reg1_we is bus_cntl:u7|tx_reg1_we at LC_X16_Y7_N0
--operation mode is normal

H1_tx_reg1_we_lut_out = H1L12 & rs & !rw_n;
H1_tx_reg1_we = DFFEAS(H1_tx_reg1_we_lut_out, GLOBAL(txclk), GLOBAL(reset), , , , , , );


--R1L6 is stsrg:u4|tx_stsrg:u1|local_tdre~39 at LC_X16_Y7_N6
--operation mode is normal

H1_tx_reg2_we_qfbk = H1_tx_reg2_we;
R1L6 = !cts & (H1_tx_reg1_we # !H1_tx_reg2_we_qfbk);

--H1_tx_reg2_we is bus_cntl:u7|tx_reg2_we at LC_X16_Y7_N6
--operation mode is normal

H1_tx_reg2_we = DFFEAS(R1L6, !GLOBAL(txclk), GLOBAL(reset), , , H1_tx_reg1_we, , , VCC);


--T1_state.ini is tcntl:u8|transm:u1|state.ini at LC_X17_Y7_N1
--operation mode is normal

T1_state.ini_lut_out = V1L52 & (R1_int_dout[2] # !T1L5);
T1_state.ini = DFFEAS(T1_state.ini_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--R1L4 is stsrg:u4|tx_stsrg:u1|int_dout[1]~45 at LC_X17_Y7_N0
--operation mode is normal

R1_int_dout[1]_qfbk = R1_int_dout[1];
R1L4 = R1_int_dout[2] & !R1_int_dout[1]_qfbk & !T1_state.ini;

--R1_int_dout[1] is stsrg:u4|tx_stsrg:u1|int_dout[1] at LC_X17_Y7_N0
--operation mode is normal

R1_int_dout[1] = DFFEAS(R1L4, !GLOBAL(txclk), GLOBAL(reset), , , cts, , , VCC);


--T1_state.stop2 is tcntl:u8|transm:u1|state.stop2 at LC_X17_Y9_N4
--operation mode is normal

T1_state.stop2_lut_out = T1_state.stop1 & G1L21 & (!G1_int_dout[1] # !G1_int_dout[0]);
T1_state.stop2 = DFFEAS(T1_state.stop2_lut_out, !GLOBAL(txclk), GLOBAL(reset), , T1L7, , , , );


--T1_state.stop1 is tcntl:u8|transm:u1|state.stop1 at LC_X17_Y10_N4
--operation mode is normal

T1_state.stop1_lut_out = !G1L01 & (V1_tc & (T1L8) # !V1_tc & T1_state.stop1);
T1_state.stop1 = DFFEAS(T1_state.stop1_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , , );


--T1L6 is tcntl:u8|transm:u1|next_state.start~253 at LC_X17_Y8_N4
--operation mode is normal

T1L6 = T1_state.stop2 # T1_state.stop1 & !G1L21;


--V1_int_dout[6] is tcntl:u8|txclkcnt:u3|int_dout[6] at LC_X16_Y8_N7
--operation mode is normal

V1_int_dout[6]_carry_eqn = (!V1L51 & V1L22) # (V1L51 & V1L32);
V1_int_dout[6]_lut_out = V1_int_dout[6] $ (!V1_int_dout[6]_carry_eqn);
V1_int_dout[6] = DFFEAS(V1_int_dout[6]_lut_out, !GLOBAL(txclk), GLOBAL(reset), , , , , V1L62, );


--V1_int_dout[5] is tcntl:u8|txclkcnt:u3|int_dout[5] at LC_X16_Y8_N6
--operation mode is arithmetic

V1_int_dout[5]_carry_eqn = (!V1L51 & V1L91) # (V1L51 & V1L02);

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