a6850.fit.summary

本文件是altera公司fpga的ip核

Flow Status : Successful - Fri Dec 23 19:42:48 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : A6850
Top-level Entity Name : a6850
Family : Cyclone
Device : EP1C3T100C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 190 / 2,910 ( 6 % )
Total pins : 31 / 65 ( 47 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )