a6850.hier_info

本文件是altera公司fpga的ip核

ce => int_dout[3].ENA
ce => int_dout[2].ENA
ce => int_dout[1].ENA
ce => int_dout[0].ENA
ce => int_dout[7].ENA
d[0] => int_dout[0].DATAIN
d[1] => int_dout[1].DATAIN
d[2] => int_dout[2].DATAIN
d[3] => int_dout[3].DATAIN
d[4] => int_dout[4].DATAIN
d[5] => int_dout[5].DATAIN
d[6] => int_dout[6].DATAIN
d[7] => int_dout[7].DATAIN
mr <= mr~0.DB_MAX_OUTPUT_PORT_TYPE
rts <= rts~0.DB_MAX_OUTPUT_PORT_TYPE
db1 <= db1~0.DB_MAX_OUTPUT_PORT_TYPE
db16 <= db16~0.DB_MAX_OUTPUT_PORT_TYPE
rx_irq_en <= int_dout[7].DB_MAX_OUTPUT_PORT_TYPE
tx_irq_en <= tx_irq_en~0.DB_MAX_OUTPUT_PORT_TYPE
break_en <= break_en~0.DB_MAX_OUTPUT_PORT_TYPE
word_lngth <= int_dout[4].DB_MAX_OUTPUT_PORT_TYPE
stop_bits <= stop_bits~6.DB_MAX_OUTPUT_PORT_TYPE
parity_en <= parity_en~1.DB_MAX_OUTPUT_PORT_TYPE
parity_odd <= parity_odd~5.DB_MAX_OUTPUT_PORT_TYPE


|A6850|bus_cntl:u7
txclk => cntl_reg1_we.CLK
txclk => dataq[7].CLK
txclk => dataq[6].CLK
txclk => dataq[5].CLK
txclk => dataq[4].CLK
txclk => dataq[3].CLK
txclk => dataq[2].CLK
txclk => dataq[1].CLK
txclk => dataq[0].CLK
txclk => tx_reg1_we.CLK
txclk => cntl_reg2_we.CLK
txclk => tx_reg2_we.CLK
rxclk => sts_reg2_re.CLK
rxclk => rx_reg2_re.CLK
rxclk => sts_reg1_re.CLK
rxclk => rx_reg1_re.CLK
clr => dataq[6].ACLR
clr => dataq[5].ACLR
clr => dataq[4].ACLR
clr => dataq[3].ACLR
clr => dataq[2].ACLR
clr => dataq[1].ACLR
clr => dataq[0].ACLR
clr => cntl_reg2_we.ACLR
clr => dataq[7].ACLR
clr => tx_reg2_we.ACLR
clr => cntl_reg1_we.ACLR
clr => tx_reg1_we.ACLR
clr => sts_reg2_re.ACLR
clr => rx_reg2_re.ACLR
clr => sts_reg1_re.ACLR
clr => rx_reg1_re.ACLR
sclr => ~NO_FANOUT~
e => we_proc~0.IN0
e => dataq[7].ENA
e => dataq[6].ENA
e => dataq[5].ENA
e => dataq[4].ENA
e => dataq[3].ENA
e => dataq[2].ENA
e => dataq[1].ENA
e => dataq[0].ENA
rs => do~0.OUTPUTSELECT
rs => do~1.OUTPUTSELECT
rs => do~2.OUTPUTSELECT
rs => do~3.OUTPUTSELECT
rs => do~4.OUTPUTSELECT
rs => do~5.OUTPUTSELECT
rs => do~6.OUTPUTSELECT
rs => do~7.OUTPUTSELECT
rs => tx_com_we.DATAB
rs => rx_com_re.DATAB
rs => cntl_com_we.DATAB
rs => sts_com_re.DATAB
rw => we_proc~2.IN1
rw => we_proc~1.IN1
cs[0] => reduce_nor~0.IN0
cs[1] => reduce_nor~0.IN1
cs[2] => reduce_nor~0.IN2
status[0] => do~7.DATAA
status[1] => do~6.DATAA
status[2] => do~5.DATAA
status[3] => do~4.DATAA
status[4] => do~3.DATAA
status[5] => do~2.DATAA
status[6] => do~1.DATAA
status[7] => do~0.DATAA
rx_data[0] => do~7.DATAB
rx_data[1] => do~6.DATAB
rx_data[2] => do~5.DATAB
rx_data[3] => do~4.DATAB
rx_data[4] => do~3.DATAB
rx_data[5] => do~2.DATAB
rx_data[6] => do~1.DATAB
rx_data[7] => do~0.DATAB
di[0] => dataq[0].DATAIN
di[1] => dataq[1].DATAIN
di[2] => dataq[2].DATAIN
di[3] => dataq[3].DATAIN
di[4] => dataq[4].DATAIN
di[5] => dataq[5].DATAIN
di[6] => dataq[6].DATAIN
di[7] => dataq[7].DATAIN
cntl_we <= cntl_we~0.DB_MAX_OUTPUT_PORT_TYPE
txreg_we <= txreg_we~0.DB_MAX_OUTPUT_PORT_TYPE
sts_re <= sts_re~0.DB_MAX_OUTPUT_PORT_TYPE
rxreg_re <= rxreg_re~0.DB_MAX_OUTPUT_PORT_TYPE
int_di[0] <= dataq[0].DB_MAX_OUTPUT_PORT_TYPE
int_di[1] <= dataq[1].DB_MAX_OUTPUT_PORT_TYPE
int_di[2] <= dataq[2].DB_MAX_OUTPUT_PORT_TYPE
int_di[3] <= dataq[3].DB_MAX_OUTPUT_PORT_TYPE
int_di[4] <= dataq[4].DB_MAX_OUTPUT_PORT_TYPE
int_di[5] <= dataq[5].DB_MAX_OUTPUT_PORT_TYPE
int_di[6] <= dataq[6].DB_MAX_OUTPUT_PORT_TYPE
int_di[7] <= dataq[7].DB_MAX_OUTPUT_PORT_TYPE
do[0] <= do~7.DB_MAX_OUTPUT_PORT_TYPE
do[1] <= do~6.DB_MAX_OUTPUT_PORT_TYPE
do[2] <= do~5.DB_MAX_OUTPUT_PORT_TYPE
do[3] <= do~4.DB_MAX_OUTPUT_PORT_TYPE
do[4] <= do~3.DB_MAX_OUTPUT_PORT_TYPE
do[5] <= do~2.DB_MAX_OUTPUT_PORT_TYPE
do[6] <= do~1.DB_MAX_OUTPUT_PORT_TYPE
do[7] <= do~0.DB_MAX_OUTPUT_PORT_TYPE


|A6850|tcntl:u8
reset => txclkcnt:u3.reset
reset => datacnt:u2.reset
reset => transm:u1.reset
txclk => txclkcnt:u3.txclk
txclk => datacnt:u2.txclk
txclk => transm:u1.txclk
mr => transm:u1.mr
parity_en => transm:u1.parity_en
stopbit2_en => transm:u1.stopbit2_en
tdre => transm:u1.tdre
cts => transm:u1.cts
db1 => txclkcnt:u3.db1
db16 => txclkcnt:u3.db16
ws2 => datacnt:u2.ws2
mux_cntl[0] <= transm:u1.mux_cntl[0]
mux_cntl[1] <= transm:u1.mux_cntl[1]
shift_en <= transm:u1.shift_en
loadsr <= transm:u1.loadsr


|A6850|tcntl:u8|transm:u1
reset => state~1.IN1
txclk => state~0.IN1
mr => next_state.ini.OUTPUTSELECT
mr => next_state.start.OUTPUTSELECT
mr => next_state.data.OUTPUTSELECT
mr => next_state.parity.OUTPUTSELECT
mr => next_state.stop1.OUTPUTSELECT
mr => next_state.stop2.OUTPUTSELECT
mr => data_cnt_en~1.OUTPUTSELECT
mr => loadsr~3.OUTPUTSELECT
mr => count_en~0.OUTPUTSELECT
mr => shift_en~0.OUTPUTSELECT
mr => clr_datacnt~2.OUTPUTSELECT
mr => clr_cnt~0.OUTPUTSELECT
mr => mux_cntl~2.OUTPUTSELECT
mr => mux_cntl~3.OUTPUTSELECT
data_tc => clr_datacnt~0.DATAB
data_tc => next_state~0.OUTPUTSELECT
data_tc => next_state~1.OUTPUTSELECT
data_tc => next_state~2.DATAB
tc => Select~2.IN1
tc => data_cnt_en~0.DATAB
tc => clr_datacnt~0.OUTPUTSELECT
tc => next_state~2.OUTPUTSELECT
tc => next_state~3.OUTPUTSELECT
tc => next_state~4.OUTPUTSELECT
tc => Select~4.IN1
tc => next_state~6.OUTPUTSELECT
tc => next_state~7.OUTPUTSELECT
tc => loadsr~1.OUTPUTSELECT
tc => Select~6.IN1
tc => next_state~8.OUTPUTSELECT
tc => loadsr~2.OUTPUTSELECT
tc => Select~1.IN6
tc => Select~3.IN3
tc => Select~4.IN5
tc => Select~5.IN3
tdre => next_state~5.DATAA
tdre => next_state~8.DATAB
tdre => statetran~0.IN0
tdre => loadsr~0.DATAA
tdre => loadsr~2.DATAB
cts => statetran~0.IN1
parity_en => next_state~0.DATAB
parity_en => next_state~1.DATAB
stopbit2_en => next_state~5.OUTPUTSELECT
stopbit2_en => next_state~7.DATAB
stopbit2_en => loadsr~0.OUTPUTSELECT
data_cnt_en <= data_cnt_en~1.DB_MAX_OUTPUT_PORT_TYPE
clr_datacnt <= clr_datacnt~2.DB_MAX_OUTPUT_PORT_TYPE
count_en <= count_en~0.DB_MAX_OUTPUT_PORT_TYPE
clr_cnt <= clr_cnt~0.DB_MAX_OUTPUT_PORT_TYPE
loadsr <= loadsr~3.DB_MAX_OUTPUT_PORT_TYPE
shift_en <= shift_en~0.DB_MAX_OUTPUT_PORT_TYPE
mux_cntl[0] <= mux_cntl~3.DB_MAX_OUTPUT_PORT_TYPE
mux_cntl[1] <= mux_cntl~2.DB_MAX_OUTPUT_PORT_TYPE


|A6850|tcntl:u8|datacnt:u2
reset => int_dout[1].ACLR
reset => int_dout[0].ACLR
reset => int_dout[2].ACLR
txclk => int_dout[1].CLK
txclk => int_dout[0].CLK
txclk => int_dout[2].CLK
clr_datacnt => mux_dout[2].OUTPUTSELECT
clr_datacnt => mux_dout[1].OUTPUTSELECT
clr_datacnt => mux_dout[0].OUTPUTSELECT
data_cnt_en => mux_dout~0.OUTPUTSELECT
data_cnt_en => mux_dout~1.OUTPUTSELECT
data_cnt_en => mux_dout~2.OUTPUTSELECT
ws2 => equal~0.IN1
data_tc <= reduce_nor~0.DB_MAX_OUTPUT_PORT_TYPE


|A6850|tcntl:u8|txclkcnt:u3
txclk => int_dout[5].CLK
txclk => int_dout[4].CLK
txclk => int_dout[3].CLK
txclk => int_dout[2].CLK
txclk => int_dout[1].CLK
txclk => int_dout[0].CLK
txclk => int_dout[6].CLK
reset => int_dout[5].ACLR
reset => int_dout[4].ACLR
reset => int_dout[3].ACLR
reset => int_dout[2].ACLR
reset => int_dout[1].ACLR
reset => int_dout[0].ACLR
reset => int_dout[6].ACLR
clr_cnt => mux_dout[6].OUTPUTSELECT
clr_cnt => mux_dout[5].OUTPUTSELECT
clr_cnt => mux_dout[4].OUTPUTSELECT
clr_cnt => mux_dout[3].OUTPUTSELECT
clr_cnt => mux_dout[2].OUTPUTSELECT
clr_cnt => mux_dout[1].OUTPUTSELECT
clr_cnt => mux_dout[0].OUTPUTSELECT
count_en => tc~0.IN0
count_en => mux_dout~0.OUTPUTSELECT
count_en => mux_dout~1.OUTPUTSELECT
count_en => mux_dout~2.OUTPUTSELECT
count_en => mux_dout~3.OUTPUTSELECT
count_en => mux_dout~4.OUTPUTSELECT
count_en => mux_dout~5.OUTPUTSELECT
count_en => mux_dout~6.OUTPUTSELECT
db1 => comp_one[5].OUTPUTSELECT
db1 => comp_one[4].OUTPUTSELECT
db1 => comb_proc~0.IN0
db1 => equal~3.IN0
db1 => equal~2.IN0
db1 => equal~1.IN0
db1 => equal~0.IN0
db16 => comp_one[5].DATAA
db16 => comp_one[4].DATAA
tc <= tc~0.DB_MAX_OUTPUT_PORT_TYPE


|A6850|srpargen:u9
reset => tshftrg:u3.reset
reset => pargen:u2.reset
txclk => tshftrg:u3.txclk
txclk => pargen:u2.txclk
parity_odd => pargen:u2.parity_odd
loadsr => tshftrg:u3.loadsr
loadsr => pargen:u2.loadsr
shift_en => tshftrg:u3.shift_en
break_en => brkmux:u5.break_en
break => brkmux:u5.break
stop => mux:u4.stop
start => mux:u4.start
ws2 => datamux:u1.ws2
sync_rst => tshftrg:u3.sync_rst
di[0] => datamux:u1.di[0]
di[1] => datamux:u1.di[1]
di[2] => datamux:u1.di[2]
di[3] => datamux:u1.di[3]
di[4] => datamux:u1.di[4]
di[5] => datamux:u1.di[5]
di[6] => datamux:u1.di[6]
di[7] => datamux:u1.di[7]
mux_cntl[0] => mux:u4.mux_cntl[0]
mux_cntl[1] => mux:u4.mux_cntl[1]
txdata <= brkmux:u5.txdata


|A6850|srpargen:u9|datamux:u1
di[0] => data[0].DATAIN
di[1] => data[1].DATAIN
di[2] => data[2].DATAIN
di[3] => data[3].DATAIN
di[4] => data[4].DATAIN
di[5] => data[5].DATAIN
di[6] => data[6].DATAIN
di[7] => data~0.DATAA
ws2 => data~0.OUTPUTSELECT
data[0] <= di[0].DB_MAX_OUTPUT_PORT_TYPE
data[1] <= di[1].DB_MAX_OUTPUT_PORT_TYPE
data[2] <= di[2].DB_MAX_OUTPUT_PORT_TYPE
data[3] <= di[3].DB_MAX_OUTPUT_PORT_TYPE
data[4] <= di[4].DB_MAX_OUTPUT_PORT_TYPE
data[5] <= di[5].DB_MAX_OUTPUT_PORT_TYPE
data[6] <= di[6].DB_MAX_OUTPUT_PORT_TYPE
data[7] <= data~0.DB_MAX_OUTPUT_PORT_TYPE


|A6850|srpargen:u9|pargen:u2
data[0] => temp_par~0.IN1
data[1] => temp_par~0.IN0
data[2] => temp_par~1.IN0
data[3] => temp_par~2.IN0
data[4] => temp_par~3.IN0
data[5] => temp_par~4.IN0
data[6] => temp_par~5.IN0
data[7] => temp_par~6.IN0
parity_odd => local_par.OUTPUTSELECT
loadsr => int_parity.ENA
txclk => int_parity.CLK
reset => int_parity.ACLR
parity <= int_parity.DB_MAX_OUTPUT_PORT_TYPE


|A6850|srpargen:u9|tshftrg:u3
txclk => data_int[6].CLK
txclk => data_int[5].CLK
txclk => data_int[4].CLK
txclk => data_int[3].CLK
txclk => data_int[2].CLK
txclk => data_int[1].CLK
txclk => data_int[0].CLK
txclk => data_int[7].CLK
reset => data_int[6].ACLR
reset => data_int[5].ACLR
reset => data_int[4].ACLR
reset => data_int[3].ACLR
reset => data_int[2].ACLR
reset => data_int[1].ACLR
reset => data_int[0].ACLR
reset => data_int[7].ACLR
data[0] => next_data~15.DATAB
data[1] => next_data~14.DATAB
data[2] => next_data~13.DATAB
data[3] => next_data~12.DATAB
data[4] => next_data~11.DATAB
data[5] => next_data~10.DATAB
data[6] => next_data~9.DATAB
data[7] => next_data~8.DATAB
sync_rst => next_data[7].OUTPUTSELECT
sync_rst => next_data[6].OUTPUTSELECT
sync_rst => next_data[5].OUTPUTSELECT
sync_rst => next_data[4].OUTPUTSELECT
sync_rst => next_data[3].OUTPUTSELECT
sync_rst => next_data[2].OUTPUTSELECT
sync_rst => next_data[1].OUTPUTSELECT
sync_rst => next_data[0].OUTPUTSELECT
shift_en => next_data~0.OUTPUTSELECT
shift_en => next_data~1.OUTPUTSELECT
shift_en => next_data~2.OUTPUTSELECT
shift_en => next_data~3.OUTPUTSELECT
shift_en => next_data~4.OUTPUTSELECT
shift_en => next_data~5.OUTPUTSELECT
shift_en => next_data~6.OUTPUTSELECT
shift_en => next_data~7.OUTPUTSELECT
loadsr => next_data~8.OUTPUTSELECT
loadsr => next_data~9.OUTPUTSELECT
loadsr => next_data~10.OUTPUTSELECT
loadsr => next_data~11.OUTPUTSELECT
loadsr => next_data~12.OUTPUTSELECT
loadsr => next_data~13.OUTPUTSELECT
loadsr => next_data~14.OUTPUTSELECT
loadsr => next_data~15.OUTPUTSELECT
data_out <= data_int[0].DB_MAX_OUTPUT_PORT_TYPE


|A6850|srpargen:u9|mux:u4
data_out => txdata1~2.DATAB
parity => txdata1~1.DATAB
stop => txdata1~0.DATAB
start => txdata1~0.DATAA
mux_cntl[0] => reduce_nor~0.IN0
mux_cntl[0] => reduce_nor~2.IN0
mux_cntl[0] => reduce_nor~1.IN0
mux_cntl[1] => reduce_nor~0.IN1
mux_cntl[1] => reduce_nor~1.IN1
mux_cntl[1] => reduce_nor~2.IN1
txdata1 <= txdata1~2.DB_MAX_OUTPUT_PORT_TYPE


|A6850|srpargen:u9|brkmux:u5
txdata1 => txdata~0.DATAB
break => txdata~0.DATAA
break_en => txdata~0.OUTPUTSELECT
txdata <= txdata~0.DB_MAX_OUTPUT_PORT_TYPE


|A6850|xmit_reg:u10
clk => int_dout[6].CLK
clk => int_dout[5].CLK
clk => int_dout[4].CLK
clk => int_dout[3].CLK
clk => int_dout[2].CLK
clk => int_dout[1].CLK
clk => int_dout[0].CLK
clk => int_dout[7].CLK
clr => int_dout[6].ACLR
clr => int_dout[5].ACLR
clr => int_dout[4].ACLR
clr => int_dout[3].ACLR
clr => int_dout[2].ACLR
clr => int_dout[1].ACLR
clr => int_dout[0].ACLR
clr => int_dout[7].ACLR
sclr => mux_dout[7].OUTPUTSELECT
sclr => mux_dout[6].OUTPUTSELECT
sclr => mux_dout[5].OUTPUTSELECT
sclr => mux_dout[4].OUTPUTSELECT
sclr => mux_dout[3].OUTPUTSELECT
sclr => mux_dout[2].OUTPUTSELECT
sclr => mux_dout[1].OUTPUTSELECT
sclr => mux_dout[0].OUTPUTSELECT
ce => mux_dout~0.OUTPUTSELECT
ce => mux_dout~1.OUTPUTSELECT
ce => mux_dout~2.OUTPUTSELECT
ce => mux_dout~3.OUTPUTSELECT
ce => mux_dout~4.OUTPUTSELECT
ce => mux_dout~5.OUTPUTSELECT
ce => mux_dout~6.OUTPUTSELECT
ce => mux_dout~7.OUTPUTSELECT
d[0] => mux_dout~7.DATAB
d[1] => mux_dout~6.DATAB
d[2] => mux_dout~5.DATAB
d[3] => mux_dout~4.DATAB
d[4] => mux_dout~3.DATAB
d[5] => mux_dout~2.DATAB
d[6] => mux_dout~1.DATAB
d[7] => mux_dout~0.DATAB
q[0] <= int_dout[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= int_dout[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= int_dout[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= int_dout[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= int_dout[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= int_dout[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= int_dout[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= int_dout[7].DB_MAX_OUTPUT_PORT_TYPE