a6850.map.qmsg

本文件是altera公司fpga的ip核

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TRANSM.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file TRANSM.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 transm-rtl " "Info: Found design unit 1: transm-rtl" {  } { { "TRANSM.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TRANSM.VHD" 58 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 transm " "Info: Found entity 1: transm" {  } { { "TRANSM.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TRANSM.VHD" 34 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TSHFTRG.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file TSHFTRG.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tshftrg-rtl " "Info: Found design unit 1: tshftrg-rtl" {  } { { "TSHFTRG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TSHFTRG.VHD" 57 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tshftrg " "Info: Found entity 1: tshftrg" {  } { { "TSHFTRG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TSHFTRG.VHD" 41 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TX_STSRG.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file TX_STSRG.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx_stsrg-rtl " "Info: Found design unit 1: tx_stsrg-rtl" {  } { { "TX_STSRG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TX_STSRG.VHD" 58 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 tx_stsrg " "Info: Found entity 1: tx_stsrg" {  } { { "TX_STSRG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TX_STSRG.VHD" 38 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TXCLKCNT.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file TXCLKCNT.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 txclkcnt-rtl " "Info: Found design unit 1: txclkcnt-rtl" {  } { { "TXCLKCNT.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TXCLKCNT.VHD" 56 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 txclkcnt " "Info: Found entity 1: txclkcnt" {  } { { "TXCLKCNT.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/TXCLKCNT.VHD" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "XMIT_REG.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file XMIT_REG.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xmit_reg-rtl " "Info: Found design unit 1: xmit_reg-rtl" {  } { { "XMIT_REG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/XMIT_REG.VHD" 54 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 xmit_reg " "Info: Found entity 1: xmit_reg" {  } { { "XMIT_REG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/XMIT_REG.VHD" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "A6850.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file A6850.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 a6850-struct " "Info: Found design unit 1: a6850-struct" {  } { { "A6850.vhd" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 56 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 a6850 " "Info: Found entity 1: a6850" {  } { { "A6850.vhd" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 33 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "A6850 " "Info: Elaborating entity \"A6850\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "ws2 A6850.vhd(65) " "Info: (10035) Verilog HDL or VHDL information at A6850.vhd(65): object \"ws2\" declared but not used" {  } { { "A6850.vhd" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 65 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rxcntl rxcntl:u1 " "Info: Elaborating entity \"rxcntl\" for hierarchy \"rxcntl:u1\"" {  } { { "A6850.vhd" "u1" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 297 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rxcntlsm rxcntl:u1\|rxcntlsm:u1 " "Info: Elaborating entity \"rxcntlsm\" for hierarchy \"rxcntl:u1\|rxcntlsm:u1\"" {  } { { "RXCNTL.VHD" "u1" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/RXCNTL.VHD" 142 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datcount rxcntl:u1\|datcount:u2 " "Info: Elaborating entity \"datcount\" for hierarchy \"rxcntl:u1\|datcount:u2\"" {  } { { "RXCNTL.VHD" "u2" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/RXCNTL.VHD" 167 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "int_tc2 DATCOUNT.VHD(61) " "Info: (10035) Verilog HDL or VHDL information at DATCOUNT.VHD(61): object \"int_tc2\" declared but not used" {  } { { "DATCOUNT.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/DATCOUNT.VHD" 61 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rxcount rxcntl:u1\|rxcount:u3 " "Info: Elaborating entity \"rxcount\" for hierarchy \"rxcntl:u1\|rxcount:u3\"" {  } { { "RXCNTL.VHD" "u3" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/RXCNTL.VHD" 177 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "framerr rxcntl:u1\|framerr:u4 " "Info: Elaborating entity \"framerr\" for hierarchy \"rxcntl:u1\|framerr:u4\"" {  } { { "RXCNTL.VHD" "u4" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/RXCNTL.VHD" 188 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "par_tree par_tree:u2 " "Info: Elaborating entity \"par_tree\" for hierarchy \"par_tree:u2\"" {  } { { "A6850.vhd" "u2" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 317 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rcv_reg rcv_reg:u3 " "Info: Elaborating entity \"rcv_reg\" for hierarchy \"rcv_reg:u3\"" {  } { { "A6850.vhd" "u3" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 329 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "stsrg stsrg:u4 " "Info: Elaborating entity \"stsrg\" for hierarchy \"stsrg:u4\"" {  } { { "A6850.vhd" "u4" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 340 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_stsrg stsrg:u4\|tx_stsrg:u1 " "Info: Elaborating entity \"tx_stsrg\" for hierarchy \"stsrg:u4\|tx_stsrg:u1\"" {  } { { "STSRG.VHD" "u1" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/STSRG.VHD" 133 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_stsrg stsrg:u4\|rx_stsrg:u2 " "Info: Elaborating entity \"rx_stsrg\" for hierarchy \"stsrg:u4\|rx_stsrg:u2\"" {  } { { "STSRG.VHD" "u2" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/STSRG.VHD" 148 -1 0 } }  } 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "duplicated signal using variable int_dout found in event expression. RX_STSRG.VHD(215) " "Warning: Verilog HDL or VHDL warning at RX_STSRG.VHD(215): duplicated signal using variable int_dout found in event expression." {  } { { "RX_STSRG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/RX_STSRG.VHD" 215 0 0 } }  } 0}
{ "Warning" "WVRFX_GENERIC_WARNING_WITH_LOC" "duplicated signal using variable int_dout found in event expression. RX_STSRG.VHD(216) " "Warning: Verilog HDL or VHDL warning at RX_STSRG.VHD(216): duplicated signal using variable int_dout found in event expression." {  } { { "RX_STSRG.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/RX_STSRG.VHD" 216 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rxshftrg rxshftrg:u5 " "Info: Elaborating entity \"rxshftrg\" for hierarchy \"rxshftrg:u5\"" {  } { { "A6850.vhd" "u5" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 365 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntl_reg cntl_reg:u6 " "Info: Elaborating entity \"cntl_reg\" for hierarchy \"cntl_reg:u6\"" {  } { { "A6850.vhd" "u6" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 383 -1 0 } }  } 0}