a6850.tan.qmsg

本文件是altera公司fpga的ip核

{ "Info" "ITDB_TH_RESULT" "bus_cntl:u7\|dataq\[0\] di\[0\] txclk -4.050 ns register " "Info: th for register \"bus_cntl:u7\|dataq\[0\]\" (data pin = \"di\[0\]\", clock pin = \"txclk\") is -4.050 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "txclk destination 2.781 ns + Longest register " "Info: + Longest clock path from clock \"txclk\" to destination register is 2.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns txclk 1 CLK PIN_10 56 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 56; CLK Node = 'txclk'" {  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "" { txclk } "NODE_NAME" } "" } } { "A6850.vhd" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.601 ns) + CELL(0.711 ns) 2.781 ns bus_cntl:u7\|dataq\[0\] 2 REG LC_X18_Y11_N2 2 " "Info: 2: + IC(0.601 ns) + CELL(0.711 ns) = 2.781 ns; Loc. = LC_X18_Y11_N2; Fanout = 2; REG Node = 'bus_cntl:u7\|dataq\[0\]'" {  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "1.312 ns" { txclk bus_cntl:u7|dataq[0] } "NODE_NAME" } "" } } { "BUS_CNTL.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/BUS_CNTL.VHD" 80 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 78.39 % " "Info: Total cell delay = 2.180 ns ( 78.39 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.601 ns 21.61 % " "Info: Total interconnect delay = 0.601 ns ( 21.61 % )" {  } {  } 0}  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "2.781 ns" { txclk bus_cntl:u7|dataq[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.781 ns" { txclk txclk~out0 bus_cntl:u7|dataq[0] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "BUS_CNTL.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/BUS_CNTL.VHD" 80 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.846 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.846 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns di\[0\] 1 PIN PIN_85 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_85; Fanout = 1; PIN Node = 'di\[0\]'" {  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "" { di[0] } "NODE_NAME" } "" } } { "A6850.vhd" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/A6850.vhd" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.062 ns) + CELL(0.309 ns) 6.846 ns bus_cntl:u7\|dataq\[0\] 2 REG LC_X18_Y11_N2 2 " "Info: 2: + IC(5.062 ns) + CELL(0.309 ns) = 6.846 ns; Loc. = LC_X18_Y11_N2; Fanout = 2; REG Node = 'bus_cntl:u7\|dataq\[0\]'" {  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "5.371 ns" { di[0] bus_cntl:u7|dataq[0] } "NODE_NAME" } "" } } { "BUS_CNTL.VHD" "" { Text "E:/genggh/001_VOB/WXY00/doc/6850_OSED/BUS_CNTL.VHD" 80 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 26.06 % " "Info: Total cell delay = 1.784 ns ( 26.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.062 ns 73.94 % " "Info: Total interconnect delay = 5.062 ns ( 73.94 % )" {  } {  } 0}  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "6.846 ns" { di[0] bus_cntl:u7|dataq[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.846 ns" { di[0] di[0]~out0 bus_cntl:u7|dataq[0] } { 0.000ns 0.000ns 5.062ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}  } { { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "2.781 ns" { txclk bus_cntl:u7|dataq[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.781 ns" { txclk txclk~out0 bus_cntl:u7|dataq[0] } { 0.000ns 0.000ns 0.601ns } { 0.000ns 1.469ns 0.711ns } } } { "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" "" { Report "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850_cmp.qrpt" Compiler "A6850" "UNKNOWN" "V1" "E:/genggh/001_VOB/WXY00/doc/6850_OSED/db/A6850.quartus_db" { Floorplan "E:/genggh/001_VOB/WXY00/doc/6850_OSED/" "" "6.846 ns" { di[0] bus_cntl:u7|dataq[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.846 ns" { di[0] di[0]~out0 bus_cntl:u7|dataq[0] } { 0.000ns 0.000ns 5.062ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 23 19:43:04 2005 " "Info: Processing ended: Fri Dec 23 19:43:04 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}