a6850.map.eqn

本文件是altera公司fpga的ip核

P1_int_dout[5] = DFFEAS(P1_int_dout[5]_lut_out, rxclk, reset, , , , , M1L2, );


--P1_int_dout[4] is rxcntl:u1|rxcount:u3|int_dout[4]
--operation mode is arithmetic

P1_int_dout[4]_carry_eqn = P1L9;
P1_int_dout[4]_lut_out = P1_int_dout[4] $ (!P1_int_dout[4]_carry_eqn);
P1_int_dout[4] = DFFEAS(P1_int_dout[4]_lut_out, rxclk, reset, , , , , M1L2, );

--P1L11 is rxcntl:u1|rxcount:u3|int_dout[4]~52
--operation mode is arithmetic

P1L11 = CARRY(P1_int_dout[4] & (!P1L9));


--P1L51 is rxcntl:u1|rxcount:u3|int_tc2~144
--operation mode is normal

P1L51 = P1_int_dout[5] & P1_int_dout[4] & (G1_int_dout[1] # !G1_int_dout[0]) # !P1_int_dout[5] & !P1_int_dout[4] & !G1_int_dout[1] & G1_int_dout[0];


--P1_int_dout[0] is rxcntl:u1|rxcount:u3|int_dout[0]
--operation mode is arithmetic

P1_int_dout[0]_lut_out = M1L6 $ P1_int_dout[0];
P1_int_dout[0] = DFFEAS(P1_int_dout[0]_lut_out, rxclk, reset, , , , , M1L2, );

--P1L3 is rxcntl:u1|rxcount:u3|int_dout[0]~56
--operation mode is arithmetic

P1L3 = CARRY(M1L6 & P1_int_dout[0]);


--P1_int_dout[1] is rxcntl:u1|rxcount:u3|int_dout[1]
--operation mode is arithmetic

P1_int_dout[1]_carry_eqn = P1L3;
P1_int_dout[1]_lut_out = P1_int_dout[1] $ (P1_int_dout[1]_carry_eqn);
P1_int_dout[1] = DFFEAS(P1_int_dout[1]_lut_out, rxclk, reset, , , , , M1L2, );

--P1L5 is rxcntl:u1|rxcount:u3|int_dout[1]~60
--operation mode is arithmetic

P1L5 = CARRY(!P1L3 # !P1_int_dout[1]);


--P1_int_dout[2] is rxcntl:u1|rxcount:u3|int_dout[2]
--operation mode is arithmetic

P1_int_dout[2]_carry_eqn = P1L5;
P1_int_dout[2]_lut_out = P1_int_dout[2] $ (!P1_int_dout[2]_carry_eqn);
P1_int_dout[2] = DFFEAS(P1_int_dout[2]_lut_out, rxclk, reset, , , , , M1L2, );

--P1L7 is rxcntl:u1|rxcount:u3|int_dout[2]~64
--operation mode is arithmetic

P1L7 = CARRY(P1_int_dout[2] & (!P1L5));


--P1L61 is rxcntl:u1|rxcount:u3|int_tc2~145
--operation mode is normal

P1L61 = P1_int_dout[0] & P1_int_dout[1] & P1_int_dout[2];


--P1L71 is rxcntl:u1|rxcount:u3|int_tc2~146
--operation mode is normal

P1L71 = P1_int_dout[3] & P1L51 & P1L61;


--M1L12 is rxcntl:u1|rxcntlsm:u1|next_state~134
--operation mode is normal

M1L12 = M1_state.wait_stop1 & M1L6 & P1L71;


--H1_dataq[2] is bus_cntl:u7|dataq[2]
--operation mode is normal

H1_dataq[2]_lut_out = di[2];
H1_dataq[2] = DFFEAS(H1_dataq[2]_lut_out, txclk, reset, , e, , , , );


--M1L71 is rxcntl:u1|rxcntlsm:u1|next_state.wait_start~157
--operation mode is normal

M1L71 = !G1L21 & (M1_state.db1_stop1 # M1_state.sample_stop1) # !M1L3;


--M1_state.wait_stop2 is rxcntl:u1|rxcntlsm:u1|state.wait_stop2
--operation mode is normal

M1_state.wait_stop2_lut_out = !G1L01 & (M1L02 # M1_state.wait_stop2 & !P1L71);
M1_state.wait_stop2 = DFFEAS(M1_state.wait_stop2_lut_out, rxclk, reset, , , , , , );


--M1L22 is rxcntl:u1|rxcntlsm:u1|next_state~135
--operation mode is normal

M1L22 = M1L6 & P1L71 & M1_state.wait_stop2;


--H1L12 is bus_cntl:u7|rx_com_re~29
--operation mode is normal

H1L12 = cs[2] & cs[1] & e & !cs[0];


--V1L81 is tcntl:u8|txclkcnt:u3|mux_dout[6]~215
--operation mode is normal

V1L81 = !G1L01 & (T1_state.ini # R1_int_dout[2] & !R1_int_dout[1]);


--T1L8 is tcntl:u8|transm:u1|next_state.stop1~188
--operation mode is normal

T1L8 = T1_state.parity # T1_state.data & U1L6 & !G1L11;


--V1L91 is tcntl:u8|txclkcnt:u3|mux_dout[6]~216
--operation mode is normal

V1L91 = V1L81 & (!V1L3 # !T1_state.ini);


--T1L2 is tcntl:u8|transm:u1|count_en~28
--operation mode is normal

T1L2 = T1_state.ini & (!G1_int_dout[0] # !G1_int_dout[1]);


--S1L01 is stsrg:u4|rx_stsrg:u2|local_data_done~72
--operation mode is normal

S1L01 = S1_int_dout[4] & S1_sts_done;


--H1_sts_reg2_re is bus_cntl:u7|sts_reg2_re
--operation mode is normal

H1_sts_reg2_re_lut_out = H1_sts_reg1_re;
H1_sts_reg2_re = DFFEAS(H1_sts_reg2_re_lut_out, rxclk, reset, , , , , , );


--H1_sts_reg1_re is bus_cntl:u7|sts_reg1_re
--operation mode is normal

H1_sts_reg1_re_lut_out = !rs & (rw_n & H1L12);
H1_sts_reg1_re = DFFEAS(H1_sts_reg1_re_lut_out, !rxclk, reset, , , , , , );


--S1L61 is stsrg:u4|rx_stsrg:u2|local_sts_done~67
--operation mode is normal

S1L61 = H1_sts_reg2_re & (!H1_sts_reg1_re);


--H1_dataq[7] is bus_cntl:u7|dataq[7]
--operation mode is normal

H1_dataq[7]_lut_out = di[7];
H1_dataq[7] = DFFEAS(H1_dataq[7]_lut_out, txclk, reset, , e, , , , );


--U1L1 is tcntl:u8|datacnt:u2|add~286
--operation mode is normal

U1L1 = T1_state.data & T1L2 & U1_int_dout[0] & !V1L3;


--T1L1 is tcntl:u8|transm:u1|clr_datacnt~47
--operation mode is normal

T1L1 = T1_state.data & U1L6 & !G1L01 & !V1L3;


--L1L5 is xmit_reg:u10|int_dout[2]~51
--operation mode is normal

L1L5 = H1_tx_reg1_we & (G1_int_dout[1] & G1_int_dout[0]) # !H1_tx_reg1_we & (H1_tx_reg2_we # G1_int_dout[1] & G1_int_dout[0]);


--Y1_data_int[2] is srpargen:u9|tshftrg:u3|data_int[2]
--operation mode is normal

Y1_data_int[2]_lut_out = !G1L01 & (T1L9 & L1_int_dout[2] # !T1L9 & (Y1_data_int[3]));
Y1_data_int[2] = DFFEAS(Y1_data_int[2]_lut_out, !txclk, reset, , Y1L4, , , , );


--M1L01 is rxcntl:u1|rxcntlsm:u1|next_state.db1_data~107
--operation mode is normal

M1L01 = !G1_int_dout[1] & !G1_int_dout[0] & !rxdata & !M1_state.wait_start;


--M1_state.wait_data is rxcntl:u1|rxcntlsm:u1|state.wait_data
--operation mode is normal

M1_state.wait_data_lut_out = M1L41 # M1L51 # M1L31 & !G1L01;
M1_state.wait_data = DFFEAS(M1_state.wait_data_lut_out, rxclk, reset, , , , , , );


--M1L42 is rxcntl:u1|rxcntlsm:u1|Select~447
--operation mode is normal

M1L42 = M1L6 & P1L71 & M1_state.wait_data;


--M1_state.wait_parity is rxcntl:u1|rxcntlsm:u1|state.wait_parity
--operation mode is normal

M1_state.wait_parity_lut_out = !G1L01 & (M1L61 # M1_state.wait_parity & !P1L71);
M1_state.wait_parity = DFFEAS(M1_state.wait_parity_lut_out, rxclk, reset, , , , , , );


--M1L52 is rxcntl:u1|rxcntlsm:u1|Select~448
--operation mode is normal

M1L52 = M1L6 & P1L71 & M1_state.wait_parity;


--M1L7 is rxcntl:u1|rxcntlsm:u1|dat_clr~145
--operation mode is normal

M1L7 = !M1_state.db1_data & !M1_state.sample_data;


--M1L8 is rxcntl:u1|rxcntlsm:u1|dat_clr~146
--operation mode is normal

M1L8 = !G1L01 & (N1L01 & !M1L7 # !M1_state.wait_start);


--M1L62 is rxcntl:u1|rxcntlsm:u1|shift_en~12
--operation mode is normal

M1L62 = G1L01 # M1L4 & !M1_state.sample_data & !M1_state.sample_parity;


--M1L81 is rxcntl:u1|rxcntlsm:u1|next_state.wait_stop1~161
--operation mode is normal

M1L81 = M1_state.wait_stop1 & (!P1L71 # !M1L6);


--M1L91 is rxcntl:u1|rxcntlsm:u1|next_state.wait_stop1~162
--operation mode is normal

M1L91 = M1_state.sample_data & N1L01 & !G1L11 & !M1L62;


--M1_state.synch is rxcntl:u1|rxcntlsm:u1|state.synch
--operation mode is normal

M1_state.synch_lut_out = M1L21 & !rxdata & (!G1_int_dout[0] # !G1_int_dout[1]);
M1_state.synch = DFFEAS(M1_state.synch_lut_out, rxclk, reset, , , , , , );


--P1L31 is rxcntl:u1|rxcount:u3|int_tc1~124
--operation mode is normal

P1L31 = P1_int_dout[4] & P1_int_dout[3] & (G1_int_dout[1] # !G1_int_dout[0]) # !P1_int_dout[4] & !P1_int_dout[3] & !G1_int_dout[1] & G1_int_dout[0];


--P1L41 is rxcntl:u1|rxcount:u3|int_tc1~125
--operation mode is normal

P1L41 = P1L61 & P1L31 & (!P1_int_dout[5]);


--M1L31 is rxcntl:u1|rxcntlsm:u1|next_state.wait_data~98
--operation mode is normal

M1L31 = M1L6 & M1_state.synch & P1L41 & !rxdata;


--M1L1 is rxcntl:u1|rxcntlsm:u1|clr_cnt~175
--operation mode is normal

M1L1 = M1L42 # M1L52 # M1L31 # !M1_state.wait_start;


--M1L2 is rxcntl:u1|rxcntlsm:u1|clr_cnt~176
--operation mode is normal

M1L2 = !G1L01 & (M1L12 # M1L22 # M1L1);


--M1L02 is rxcntl:u1|rxcntlsm:u1|next_state.wait_stop2~203
--operation mode is normal

M1L02 = M1_state.sample_stop1 & !G1_int_dout[3] & (!G1_int_dout[2] # !G1_int_dout[4]);


--Y1_data_int[3] is srpargen:u9|tshftrg:u3|data_int[3]
--operation mode is normal

Y1_data_int[3]_lut_out = !G1L01 & (T1L9 & L1_int_dout[3] # !T1L9 & (Y1_data_int[4]));
Y1_data_int[3] = DFFEAS(Y1_data_int[3]_lut_out, !txclk, reset, , Y1L4, , , , );


--M1L41 is rxcntl:u1|rxcntlsm:u1|next_state.wait_data~99
--operation mode is normal

M1L41 = M1_state.wait_data & !G1L01 & (!P1L71 # !M1L6);


--M1L51 is rxcntl:u1|rxcntlsm:u1|next_state.wait_data~100
--operation mode is normal

M1L51 = M1_state.sample_data & !G1L01 & (M1L62 # !N1L01);


--M1L61 is rxcntl:u1|rxcntlsm:u1|next_state.wait_parity~219
--operation mode is normal

M1L61 = G1L11 & M1_state.sample_data & N1L01 & !G1L01;


--M1L21 is rxcntl:u1|rxcntlsm:u1|next_state.synch~205
--operation mode is normal

M1L21 = M1_state.synch & (!M1L9 & !M1_state.wait_start # !P1L41) # !M1_state.synch & !M1L9 & !M1_state.wait_start;


--Y1_data_int[4] is srpargen:u9|tshftrg:u3|data_int[4]
--operation mode is normal

Y1_data_int[4]_lut_out = !G1L01 & (T1L9 & L1_int_dout[4] # !T1L9 & (Y1_data_int[5]));
Y1_data_int[4] = DFFEAS(Y1_data_int[4]_lut_out, !txclk, reset, , Y1L4, , , , );


--Y1_data_int[5] is srpargen:u9|tshftrg:u3|data_int[5]
--operation mode is normal

Y1_data_int[5]_lut_out = !G1L01 & (T1L9 & L1_int_dout[5] # !T1L9 & (Y1_data_int[6]));
Y1_data_int[5] = DFFEAS(Y1_data_int[5]_lut_out, !txclk, reset, , Y1L4, , , , );


--Y1_data_int[6] is srpargen:u9|tshftrg:u3|data_int[6]
--operation mode is normal

Y1_data_int[6]_lut_out = !G1L01 & (T1L9 & L1_int_dout[6] # !T1L9 & (Y1_data_int[7]));
Y1_data_int[6] = DFFEAS(Y1_data_int[6]_lut_out, !txclk, reset, , Y1L4, , , , );


--Y1_data_int[7] is srpargen:u9|tshftrg:u3|data_int[7]
--operation mode is normal

Y1_data_int[7]_lut_out = T1L3 & (W1L1 # !Y1L4 & Y1_data_int[7]) # !T1L3 & !Y1L4 & Y1_data_int[7];
Y1_data_int[7] = DFFEAS(Y1_data_int[7]_lut_out, !txclk, reset, , , , , , );


--S1L41 is stsrg:u4|rx_stsrg:u2|local_ovr~146
--operation mode is normal

S1L41 = M1L32 # G1_int_dout[1] & G1_int_dout[0];


--rs is rs
--operation mode is input

rs = INPUT();


--rxclk is rxclk
--operation mode is input

rxclk = INPUT();


--reset is reset
--operation mode is input

reset = INPUT();


--cts is cts
--operation mode is input

cts = INPUT();


--txclk is txclk
--operation mode is input

txclk = INPUT();


--dcd is dcd
--operation mode is input

dcd = INPUT();


--rxdata is rxdata
--operation mode is input

rxdata = INPUT();


--rw_n is rw_n
--operation mode is input

rw_n = INPUT();


--cs[2] is cs[2]
--operation mode is input

cs[2] = INPUT();


--cs[1] is cs[1]
--operation mode is input

cs[1] = INPUT();


--e is e
--operation mode is input

e = INPUT();


--cs[0] is cs[0]
--operation mode is input

cs[0] = INPUT();


--di[6] is di[6]
--operation mode is input

di[6] = INPUT();


--di[5] is di[5]
--operation mode is input

di[5] = INPUT();


--di[1] is di[1]
--operation mode is input

di[1] = INPUT();


--di[0] is di[0]
--operation mode is input

di[0] = INPUT();


--di[3] is di[3]
--operation mode is input

di[3] = INPUT();


--di[4] is di[4]
--operation mode is input

di[4] = INPUT();


--di[2] is di[2]
--operation mode is input

di[2] = INPUT();


--di[7] is di[7]
--operation mode is input

di[7] = INPUT();


--do[0] is do[0]
--operation mode is output

do[0] = OUTPUT(H1L31);


--do[1] is do[1]
--operation mode is output

do[1] = OUTPUT(H1L41);


--do[2] is do[2]
--operation mode is output

do[2] = OUTPUT(H1L51);


--do[3] is do[3]
--operation mode is output

do[3] = OUTPUT(H1L61);


--do[4] is do[4]
--operation mode is output

do[4] = OUTPUT(H1L71);


--do[5] is do[5]
--operation mode is output

do[5] = OUTPUT(H1L81);


--do[6] is do[6]
--operation mode is output

do[6] = OUTPUT(H1L91);


--do[7] is do[7]
--operation mode is output

do[7] = OUTPUT(H1L02);


--irq_n is irq_n
--operation mode is output

irq_n = OUTPUT(!E1_sts_reg[7]);


--txdata is txdata
--operation mode is output

txdata = OUTPUT(AB1L3);


--rts is rts
--operation mode is output

rts = OUTPUT(G1L31);