a6850.map.eqn

本文件是altera公司fpga的ip核

--operation mode is arithmetic

V1_int_dout[3]_carry_eqn = V1L01;
V1_int_dout[3]_lut_out = V1_int_dout[3] $ (V1_int_dout[3]_carry_eqn);
V1_int_dout[3] = DFFEAS(V1_int_dout[3]_lut_out, !txclk, reset, , , , , V1L91, );

--V1L21 is tcntl:u8|txclkcnt:u3|int_dout[3]~75
--operation mode is arithmetic

V1L21 = CARRY(!V1L01 # !V1_int_dout[3]);


--V1L2 is tcntl:u8|txclkcnt:u3|comb_proc~245
--operation mode is normal

V1L2 = V1_int_dout[0] & V1_int_dout[1] & V1_int_dout[2] & V1_int_dout[3];


--M1L9 is rxcntl:u1|rxcntlsm:u1|next_state.db1_data~106
--operation mode is normal

M1L9 = !G1_int_dout[1] & !G1_int_dout[0];


--V1L3 is tcntl:u8|txclkcnt:u3|comb_proc~246
--operation mode is normal

V1L3 = !M1L9 & (V1_int_dout[6] # !V1L2 # !V1L1);


--V1_tc is tcntl:u8|txclkcnt:u3|tc
--operation mode is normal

V1_tc = T1_state.ini & !V1L3 & (!G1_int_dout[0] # !G1_int_dout[1]);


--T1L9 is tcntl:u8|transm:u1|Select~358
--operation mode is normal

T1L9 = R1L4 # R1_int_dout[2] & T1L6 & V1_tc;


--R1L7 is stsrg:u4|tx_stsrg:u1|local_tdre~40
--operation mode is normal

R1L7 = G1L01 # R1L6 & (T1L9 # !R1_int_dout[2]);


--F1_data[3] is rxshftrg:u5|data[3]
--operation mode is normal

F1_data[3]_lut_out = F1_data[4] & (!G1_int_dout[0] # !G1_int_dout[1]);
F1_data[3] = DFFEAS(F1_data[3]_lut_out, rxclk, reset, , F1L6, , , , );


--F1L41 is rxshftrg:u5|par_out[2]~659
--operation mode is normal

F1L41 = G1_int_dout[3] & (G1_int_dout[4] & F1_data[2] # !G1_int_dout[4] & (F1_data[3])) # !G1_int_dout[3] & (F1_data[3]);


--S1_data_done is stsrg:u4|rx_stsrg:u2|data_done
--operation mode is normal

S1_data_done_lut_out = !G1L01 & (S1_data_done # S1L9 & S1L01);
S1_data_done = DFFEAS(S1_data_done_lut_out, rxclk, reset, , , , , , );


--S1_sts_done is stsrg:u4|rx_stsrg:u2|sts_done
--operation mode is normal

S1_sts_done_lut_out = !G1L01 & (S1_sts_done # S1_int_dout[4] & S1L61);
S1_sts_done = DFFEAS(S1_sts_done_lut_out, rxclk, reset, , , , , , );


--S1L11 is stsrg:u4|rx_stsrg:u2|local_dcd~119
--operation mode is normal

S1L11 = !S1_sts_done # !S1_data_done;


--S1L21 is stsrg:u4|rx_stsrg:u2|local_dcd~120
--operation mode is normal

S1L21 = dcd # S1_int_dout[4] & S1L11 & !G1L01;


--F1_data[4] is rxshftrg:u5|data[4]
--operation mode is normal

F1_data[4]_lut_out = F1_data[5] & (!G1_int_dout[0] # !G1_int_dout[1]);
F1_data[4] = DFFEAS(F1_data[4]_lut_out, rxclk, reset, , F1L6, , , , );


--F1L51 is rxshftrg:u5|par_out[3]~660
--operation mode is normal

F1L51 = G1_int_dout[3] & (G1_int_dout[4] & F1_data[3] # !G1_int_dout[4] & (F1_data[4])) # !G1_int_dout[3] & (F1_data[4]);


--F1_data[5] is rxshftrg:u5|data[5]
--operation mode is normal

F1_data[5]_lut_out = F1_data[6] & (!G1_int_dout[0] # !G1_int_dout[1]);
F1_data[5] = DFFEAS(F1_data[5]_lut_out, rxclk, reset, , F1L6, , , , );


--F1L61 is rxshftrg:u5|par_out[4]~661
--operation mode is normal

F1L61 = G1_int_dout[3] & (G1_int_dout[4] & F1_data[4] # !G1_int_dout[4] & (F1_data[5])) # !G1_int_dout[3] & (F1_data[5]);


--Q1_int_dout is rxcntl:u1|framerr:u4|int_dout
--operation mode is normal

Q1_int_dout_lut_out = !G1L01 & (Q1_int_dout # A1L92 & !rxdata);
Q1_int_dout = DFFEAS(Q1_int_dout_lut_out, rxclk, reset, , , , , , );


--A1L03 is rtl~372
--operation mode is normal

A1L03 = G1L21 & Q1_int_dout # !G1L21 & (A1L92 & !rxdata);


--F1_data[6] is rxshftrg:u5|data[6]
--operation mode is normal

F1_data[6]_lut_out = F1_data[7] & (!G1_int_dout[0] # !G1_int_dout[1]);
F1_data[6] = DFFEAS(F1_data[6]_lut_out, rxclk, reset, , F1L6, , , , );


--F1L71 is rxshftrg:u5|par_out[5]~662
--operation mode is normal

F1L71 = G1_int_dout[3] & (G1_int_dout[4] & F1_data[5] # !G1_int_dout[4] & (F1_data[6])) # !G1_int_dout[3] & (F1_data[6]);


--S1L31 is stsrg:u4|rx_stsrg:u2|local_ovr~145
--operation mode is normal

S1L31 = !G1L01 & (M1L32 & M1_state.overrun # !M1L32 & (S1_int_dout[2]));


--F1_data[7] is rxshftrg:u5|data[7]
--operation mode is normal

F1_data[7]_lut_out = F1_data[8] & (!G1_int_dout[0] # !G1_int_dout[1]);
F1_data[7] = DFFEAS(F1_data[7]_lut_out, rxclk, reset, , F1L6, , , , );


--F1L81 is rxshftrg:u5|par_out[6]~663
--operation mode is normal

F1L81 = G1_int_dout[3] & (G1_int_dout[4] & F1_data[6] # !G1_int_dout[4] & (F1_data[7])) # !G1_int_dout[3] & (F1_data[7]);


--G1L11 is cntl_reg:u6|stop_bits~4
--operation mode is normal

G1L11 = G1_int_dout[3] # !G1_int_dout[4];


--C1L1 is par_tree:u2|parity_err~105
--operation mode is normal

C1L1 = F1L21 $ F1L31 $ F1L41 $ F1L51;


--F1_data[8] is rxshftrg:u5|data[8]
--operation mode is normal

F1_data[8]_lut_out = rxdata & (!G1_int_dout[0] # !G1_int_dout[1]);
F1_data[8] = DFFEAS(F1_data[8]_lut_out, rxclk, reset, , F1L6, , , , );


--F1L91 is rxshftrg:u5|par_out[7]~664
--operation mode is normal

F1L91 = G1_int_dout[4] & (G1_int_dout[3] & F1_data[7] # !G1_int_dout[3] & (F1_data[8]));


--C1L2 is par_tree:u2|parity_err~106
--operation mode is normal

C1L2 = F1L61 $ F1L71 $ F1L81 $ F1L91;


--C1L3 is par_tree:u2|parity_err~107
--operation mode is normal

C1L3 = F1_data[8] $ C1L2 $ (G1_int_dout[2] & G1L11);


--G1_int_dout[7] is cntl_reg:u6|int_dout[7]
--operation mode is normal

G1_int_dout[7]_lut_out = H1_dataq[7];
G1_int_dout[7] = DFFEAS(G1_int_dout[7]_lut_out, !txclk, reset, , H1_cntl_we, , , , );


--H1_dataq[6] is bus_cntl:u7|dataq[6]
--operation mode is normal

H1_dataq[6]_lut_out = di[6];
H1_dataq[6] = DFFEAS(H1_dataq[6]_lut_out, txclk, reset, , e, , , , );


--H1_cntl_reg2_we is bus_cntl:u7|cntl_reg2_we
--operation mode is normal

H1_cntl_reg2_we_lut_out = H1_cntl_reg1_we;
H1_cntl_reg2_we = DFFEAS(H1_cntl_reg2_we_lut_out, !txclk, reset, , , , , , );


--H1_cntl_reg1_we is bus_cntl:u7|cntl_reg1_we
--operation mode is normal

H1_cntl_reg1_we_lut_out = !rs & !rw_n & (H1L12);
H1_cntl_reg1_we = DFFEAS(H1_cntl_reg1_we_lut_out, txclk, reset, , , , , , );


--H1_cntl_we is bus_cntl:u7|cntl_we
--operation mode is normal

H1_cntl_we = H1_cntl_reg2_we & (!H1_cntl_reg1_we);


--H1_dataq[5] is bus_cntl:u7|dataq[5]
--operation mode is normal

H1_dataq[5]_lut_out = di[5];
H1_dataq[5] = DFFEAS(H1_dataq[5]_lut_out, txclk, reset, , e, , , , );


--H1_dataq[1] is bus_cntl:u7|dataq[1]
--operation mode is normal

H1_dataq[1]_lut_out = di[1];
H1_dataq[1] = DFFEAS(H1_dataq[1]_lut_out, txclk, reset, , e, , , , );


--H1_dataq[0] is bus_cntl:u7|dataq[0]
--operation mode is normal

H1_dataq[0]_lut_out = di[0];
H1_dataq[0] = DFFEAS(H1_dataq[0]_lut_out, txclk, reset, , e, , , , );


--U1_int_dout[1] is tcntl:u8|datacnt:u2|int_dout[1]
--operation mode is normal

U1_int_dout[1]_lut_out = !T1L1 & (U1_int_dout[1] $ U1L1);
U1_int_dout[1] = DFFEAS(U1_int_dout[1]_lut_out, !txclk, reset, , , , , , );


--U1_int_dout[2] is tcntl:u8|datacnt:u2|int_dout[2]
--operation mode is normal

U1_int_dout[2]_lut_out = !T1L1 & (U1_int_dout[2] $ (U1_int_dout[1] & U1L1));
U1_int_dout[2] = DFFEAS(U1_int_dout[2]_lut_out, !txclk, reset, , , , , , );


--U1_int_dout[0] is tcntl:u8|datacnt:u2|int_dout[0]
--operation mode is normal

U1_int_dout[0]_lut_out = !T1L1 & (U1_int_dout[0] $ (T1_state.data & V1_tc));
U1_int_dout[0] = DFFEAS(U1_int_dout[0]_lut_out, !txclk, reset, , , , , , );


--U1L6 is tcntl:u8|datacnt:u2|reduce_nor~25
--operation mode is normal

U1L6 = U1_int_dout[1] & U1_int_dout[2] & (G1_int_dout[4] $ !U1_int_dout[0]);


--T1L7 is tcntl:u8|transm:u1|next_state.start~254
--operation mode is normal

T1L7 = V1L3 & (G1_int_dout[1] & G1_int_dout[0]) # !V1L3 & (T1_state.ini # G1_int_dout[1] & G1_int_dout[0]);


--L1_int_dout[7] is xmit_reg:u10|int_dout[7]
--operation mode is normal

L1_int_dout[7]_lut_out = H1_dataq[7] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[7] = DFFEAS(L1_int_dout[7]_lut_out, !txclk, reset, , L1L5, , , , );


--W1L1 is srpargen:u9|datamux:u1|data[7]~9
--operation mode is normal

W1L1 = G1_int_dout[4] & L1_int_dout[7];


--L1_int_dout[0] is xmit_reg:u10|int_dout[0]
--operation mode is normal

L1_int_dout[0]_lut_out = H1_dataq[0] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[0] = DFFEAS(L1_int_dout[0]_lut_out, !txclk, reset, , L1L5, , , , );


--L1_int_dout[6] is xmit_reg:u10|int_dout[6]
--operation mode is normal

L1_int_dout[6]_lut_out = H1_dataq[6] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[6] = DFFEAS(L1_int_dout[6]_lut_out, !txclk, reset, , L1L5, , , , );


--L1_int_dout[5] is xmit_reg:u10|int_dout[5]
--operation mode is normal

L1_int_dout[5]_lut_out = H1_dataq[5] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[5] = DFFEAS(L1_int_dout[5]_lut_out, !txclk, reset, , L1L5, , , , );


--L1_int_dout[4] is xmit_reg:u10|int_dout[4]
--operation mode is normal

L1_int_dout[4]_lut_out = H1_dataq[4] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[4] = DFFEAS(L1_int_dout[4]_lut_out, !txclk, reset, , L1L5, , , , );


--X1L1 is srpargen:u9|pargen:u2|local_par~54
--operation mode is normal

X1L1 = L1_int_dout[0] $ L1_int_dout[6] $ L1_int_dout[5] $ L1_int_dout[4];


--L1_int_dout[3] is xmit_reg:u10|int_dout[3]
--operation mode is normal

L1_int_dout[3]_lut_out = H1_dataq[3] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[3] = DFFEAS(L1_int_dout[3]_lut_out, !txclk, reset, , L1L5, , , , );


--L1_int_dout[2] is xmit_reg:u10|int_dout[2]
--operation mode is normal

L1_int_dout[2]_lut_out = H1_dataq[2] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[2] = DFFEAS(L1_int_dout[2]_lut_out, !txclk, reset, , L1L5, , , , );


--L1_int_dout[1] is xmit_reg:u10|int_dout[1]
--operation mode is normal

L1_int_dout[1]_lut_out = H1_dataq[1] & (!G1_int_dout[0] # !G1_int_dout[1]);
L1_int_dout[1] = DFFEAS(L1_int_dout[1]_lut_out, !txclk, reset, , L1L5, , , , );


--X1L2 is srpargen:u9|pargen:u2|local_par~55
--operation mode is normal

X1L2 = X1L1 $ L1_int_dout[3] $ L1_int_dout[2] $ L1_int_dout[1];


--T1L5 is tcntl:u8|transm:u1|next_state.ini~222
--operation mode is normal

T1L5 = T1_state.ini & T1L6 & !G1L01 & !V1L3;


--T1L3 is tcntl:u8|transm:u1|loadsr~90
--operation mode is normal

T1L3 = !G1L01 & (R1L4 # R1_int_dout[2] & T1L5);


--T1L4 is tcntl:u8|transm:u1|next_state.data~145
--operation mode is normal

T1L4 = T1_state.data & !G1L01 & (V1L3 # !U1L6);


--Y1_data_int[1] is srpargen:u9|tshftrg:u3|data_int[1]
--operation mode is normal

Y1_data_int[1]_lut_out = !G1L01 & (T1L9 & L1_int_dout[1] # !T1L9 & (Y1_data_int[2]));
Y1_data_int[1] = DFFEAS(Y1_data_int[1]_lut_out, !txclk, reset, , Y1L4, , , , );


--Y1L4 is srpargen:u9|tshftrg:u3|data_int[1]~55
--operation mode is normal

Y1L4 = G1L01 # T1L9 # T1_state.data & V1_tc;


--M1_state.db1_parity is rxcntl:u1|rxcntlsm:u1|state.db1_parity
--operation mode is normal

M1_state.db1_parity_lut_out = G1L11 & M1_state.db1_data & N1L01 & !G1L01;
M1_state.db1_parity = DFFEAS(M1_state.db1_parity_lut_out, rxclk, reset, , , , , , );


--M1_state.db1_data is rxcntl:u1|rxcntlsm:u1|state.db1_data
--operation mode is normal

M1_state.db1_data_lut_out = !G1L01 & (M1L01 # M1_state.db1_data & !N1L01);
M1_state.db1_data = DFFEAS(M1_state.db1_data_lut_out, rxclk, reset, , , , , , );


--M1L4 is rxcntl:u1|rxcntlsm:u1|cnt_en~71
--operation mode is normal

M1L4 = !M1_state.db1_parity & !M1_state.db1_data;


--M1_state.sample_data is rxcntl:u1|rxcntlsm:u1|state.sample_data
--operation mode is normal

M1_state.sample_data_lut_out = M1L42;
M1_state.sample_data = DFFEAS(M1_state.sample_data_lut_out, rxclk, reset, , , , , , );


--M1_state.sample_parity is rxcntl:u1|rxcntlsm:u1|state.sample_parity
--operation mode is normal

M1_state.sample_parity_lut_out = M1L52;
M1_state.sample_parity = DFFEAS(M1_state.sample_parity_lut_out, rxclk, reset, , , , , , );


--F1L6 is rxshftrg:u5|data[3]~66
--operation mode is normal

F1L6 = G1L01 # M1_state.sample_data # M1_state.sample_parity # !M1L4;


--H1_dataq[3] is bus_cntl:u7|dataq[3]
--operation mode is normal

H1_dataq[3]_lut_out = di[3];
H1_dataq[3] = DFFEAS(H1_dataq[3]_lut_out, txclk, reset, , e, , , , );


--H1_dataq[4] is bus_cntl:u7|dataq[4]
--operation mode is normal

H1_dataq[4]_lut_out = di[4];
H1_dataq[4] = DFFEAS(H1_dataq[4]_lut_out, txclk, reset, , e, , , , );


--N1_int_dout[1] is rxcntl:u1|datcount:u2|int_dout[1]
--operation mode is arithmetic

N1_int_dout[1]_carry_eqn = N1L3;
N1_int_dout[1]_lut_out = N1_int_dout[1] $ (N1_int_dout[1]_carry_eqn);
N1_int_dout[1] = DFFEAS(N1_int_dout[1]_lut_out, rxclk, reset, , , , , M1L8, );

--N1L5 is rxcntl:u1|datcount:u2|int_dout[1]~30
--operation mode is arithmetic

N1L5 = CARRY(!N1L3 # !N1_int_dout[1]);


--N1_int_dout[2] is rxcntl:u1|datcount:u2|int_dout[2]
--operation mode is arithmetic

N1_int_dout[2]_carry_eqn = N1L5;
N1_int_dout[2]_lut_out = N1_int_dout[2] $ (!N1_int_dout[2]_carry_eqn);
N1_int_dout[2] = DFFEAS(N1_int_dout[2]_lut_out, rxclk, reset, , , , , M1L8, );

--N1L7 is rxcntl:u1|datcount:u2|int_dout[2]~34
--operation mode is arithmetic

N1L7 = CARRY(N1_int_dout[2] & (!N1L5));


--N1_int_dout[3] is rxcntl:u1|datcount:u2|int_dout[3]
--operation mode is normal

N1_int_dout[3]_carry_eqn = N1L7;
N1_int_dout[3]_lut_out = N1_int_dout[3] $ (N1_int_dout[3]_carry_eqn);
N1_int_dout[3] = DFFEAS(N1_int_dout[3]_lut_out, rxclk, reset, , , , , M1L8, );


--N1_int_dout[0] is rxcntl:u1|datcount:u2|int_dout[0]
--operation mode is arithmetic

N1_int_dout[0]_lut_out = M1L62 $ !N1_int_dout[0];
N1_int_dout[0] = DFFEAS(N1_int_dout[0]_lut_out, rxclk, reset, , , , , M1L8, );

--N1L3 is rxcntl:u1|datcount:u2|int_dout[0]~42
--operation mode is arithmetic

N1L3 = CARRY(!M1L62 & N1_int_dout[0]);


--N1L9 is rxcntl:u1|datcount:u2|int_tc1~18
--operation mode is normal

N1L9 = N1_int_dout[0] $ G1_int_dout[4];


--N1L01 is rxcntl:u1|datcount:u2|tc1~111
--operation mode is normal

N1L01 = N1_int_dout[1] & N1_int_dout[2] & !N1_int_dout[3] & !N1L9;


--M1L11 is rxcntl:u1|rxcntlsm:u1|next_state.db1_stop1~68
--operation mode is normal

M1L11 = G1_int_dout[4] & M1_state.db1_data & (!G1_int_dout[3]);


--M1_state.wait_stop1 is rxcntl:u1|rxcntlsm:u1|state.wait_stop1
--operation mode is normal

M1_state.wait_stop1_lut_out = !G1L01 & (M1_state.sample_parity # M1L81 # M1L91);
M1_state.wait_stop1 = DFFEAS(M1_state.wait_stop1_lut_out, rxclk, reset, , , , , , );


--M1L5 is rxcntl:u1|rxcntlsm:u1|cnt_en~72
--operation mode is normal

M1L5 = !M1_state.db1_parity & !M1_state.db1_data & (!G1_int_dout[0] # !G1_int_dout[1]);


--M1_state.wait_start is rxcntl:u1|rxcntlsm:u1|state.wait_start
--operation mode is normal

M1_state.wait_start_lut_out = !S1L41 & (!M1_state.synch & M1_state.wait_start # !rxdata);
M1_state.wait_start = DFFEAS(M1_state.wait_start_lut_out, rxclk, reset, , , , , , );


--M1L6 is rxcntl:u1|rxcntlsm:u1|cnt_en~73
--operation mode is normal

M1L6 = M1L3 & M1L5 & M1_state.wait_start & !M1_state.db1_stop1;


--P1_int_dout[3] is rxcntl:u1|rxcount:u3|int_dout[3]
--operation mode is arithmetic

P1_int_dout[3]_carry_eqn = P1L7;
P1_int_dout[3]_lut_out = P1_int_dout[3] $ (P1_int_dout[3]_carry_eqn);
P1_int_dout[3] = DFFEAS(P1_int_dout[3]_lut_out, rxclk, reset, , , , , M1L2, );

--P1L9 is rxcntl:u1|rxcount:u3|int_dout[3]~44
--operation mode is arithmetic

P1L9 = CARRY(!P1L7 # !P1_int_dout[3]);


--P1_int_dout[5] is rxcntl:u1|rxcount:u3|int_dout[5]
--operation mode is normal

P1_int_dout[5]_carry_eqn = P1L11;
P1_int_dout[5]_lut_out = P1_int_dout[5] $ (P1_int_dout[5]_carry_eqn);