a6850.qsf

本文件是altera公司fpga的ip核

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		A6850_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:39:37  DECEMBER 23, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VHDL_FILE BRKMUX.VHD
set_global_assignment -name VHDL_FILE BUS_CNTL.VHD
set_global_assignment -name VHDL_FILE CNTL_REG.VHD
set_global_assignment -name VHDL_FILE DATACNT.VHD
set_global_assignment -name VHDL_FILE DATAMUX.VHD
set_global_assignment -name VHDL_FILE DATCOUNT.VHD
set_global_assignment -name VHDL_FILE FRAMERR.VHD
set_global_assignment -name VHDL_FILE MUX.VHD
set_global_assignment -name VHDL_FILE PAR_TREE.VHD
set_global_assignment -name VHDL_FILE PARGEN.VHD
set_global_assignment -name VHDL_FILE RCV_REG.VHD
set_global_assignment -name VHDL_FILE RX_STSRG.VHD
set_global_assignment -name VHDL_FILE RXCNTL.VHD
set_global_assignment -name VHDL_FILE RXCNTLSM.VHD
set_global_assignment -name VHDL_FILE RXCOUNT.VHD
set_global_assignment -name VHDL_FILE RXSHFTRG.VHD
set_global_assignment -name VHDL_FILE SRPARGEN.VHD
set_global_assignment -name VHDL_FILE STSRG.VHD
set_global_assignment -name VHDL_FILE TCNTL.VHD
set_global_assignment -name VHDL_FILE TRANSM.VHD
set_global_assignment -name VHDL_FILE TSHFTRG.VHD
set_global_assignment -name VHDL_FILE TX_STSRG.VHD
set_global_assignment -name VHDL_FILE TXCLKCNT.VHD
set_global_assignment -name VHDL_FILE XMIT_REG.VHD
set_global_assignment -name VHDL_FILE A6850.vhd

# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"

# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<NONE>"
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY A6850

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T100C8
set_global_assignment -name OPTIMIZE_TIMING NORMAL_COMPILATION
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX NORMAL
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "<NONE>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>"

# Assembler Assignments
# =====================
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name EXCALIBUR_CONFIGURATION_DEVICE EPC2
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE EPC2
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE EPC1
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE EPC2
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPC2
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF