a6850.tan.rpt

本文件是altera公司fpga的ip核

Timing Analyzer report for A6850
Fri Dec 23 19:43:04 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'rxclk'
  6. Clock Setup: 'txclk'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                 ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------------+----------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                ; To                               ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------------+----------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 7.954 ns                         ; rxdata                              ; rxcntl:u1|rxcount:u3|int_dout[4] ;            ; rxclk    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 11.735 ns                        ; tcntl:u8|transm:u1|state.data       ; txdata                           ; txclk      ;          ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 12.381 ns                        ; rs                                  ; do[7]                            ;            ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; -4.050 ns                        ; di[0]                               ; bus_cntl:u7|dataq[0]             ;            ; txclk    ; 0            ;
; Clock Setup: 'rxclk'         ; N/A   ; None          ; 158.38 MHz ( period = 6.314 ns ) ; rxcntl:u1|rxcntlsm:u1|state.overrun ; rxcntl:u1|rxcount:u3|int_dout[3] ; rxclk      ; rxclk    ; 0            ;
; Clock Setup: 'txclk'         ; N/A   ; None          ; 160.03 MHz ( period = 6.249 ns ) ; cntl_reg:u6|int_dout[1]             ; tcntl:u8|txclkcnt:u3|int_dout[6] ; txclk      ; txclk    ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                     ;                                  ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+-------------------------------------+----------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;