a6850.map.rpt

本文件是altera公司fpga的ip核

Info: Found 2 design units, including 1 entities, in source file DATCOUNT.VHD
    Info: Found design unit 1: datcount-rtl
    Info: Found entity 1: datcount
Info: Found 2 design units, including 1 entities, in source file FRAMERR.VHD
    Info: Found design unit 1: framerr-rtl
    Info: Found entity 1: framerr
Warning: Entity "mux" obtained from "E:/genggh/001_VOB/WXY00/doc/6850_OSED/MUX.VHD" instead of from Quartus II megafunction library
Info: Found 2 design units, including 1 entities, in source file MUX.VHD
    Info: Found design unit 1: mux-rtl
    Info: Found entity 1: mux
Info: Found 2 design units, including 1 entities, in source file PAR_TREE.VHD
    Info: Found design unit 1: par_tree-rtl
    Info: Found entity 1: par_tree
Info: Found 2 design units, including 1 entities, in source file PARGEN.VHD
    Info: Found design unit 1: pargen-rtl
    Info: Found entity 1: pargen
Info: Found 2 design units, including 1 entities, in source file RCV_REG.VHD
    Info: Found design unit 1: rcv_reg-rtl
    Info: Found entity 1: rcv_reg
Info: Found 2 design units, including 1 entities, in source file RX_STSRG.VHD
    Info: Found design unit 1: rx_stsrg-rtl
    Info: Found entity 1: rx_stsrg
Info: Found 2 design units, including 1 entities, in source file RXCNTL.VHD
    Info: Found design unit 1: rxcntl-struct
    Info: Found entity 1: rxcntl
Info: Found 2 design units, including 1 entities, in source file RXCNTLSM.VHD
    Info: Found design unit 1: rxcntlsm-rtl
    Info: Found entity 1: rxcntlsm
Info: Found 2 design units, including 1 entities, in source file RXCOUNT.VHD
    Info: Found design unit 1: rxcount-rtl
    Info: Found entity 1: rxcount
Info: Found 2 design units, including 1 entities, in source file RXSHFTRG.VHD
    Info: Found design unit 1: rxshftrg-rtl
    Info: Found entity 1: rxshftrg
Info: Found 2 design units, including 1 entities, in source file SRPARGEN.VHD
    Info: Found design unit 1: srpargen-struct
    Info: Found entity 1: srpargen
Info: Found 2 design units, including 1 entities, in source file STSRG.VHD
    Info: Found design unit 1: stsrg-struct
    Info: Found entity 1: stsrg
Info: Found 2 design units, including 1 entities, in source file TCNTL.VHD
    Info: Found design unit 1: tcntl-struct
    Info: Found entity 1: tcntl
Info: Found 2 design units, including 1 entities, in source file TRANSM.VHD
    Info: Found design unit 1: transm-rtl
    Info: Found entity 1: transm
Info: Found 2 design units, including 1 entities, in source file TSHFTRG.VHD
    Info: Found design unit 1: tshftrg-rtl
    Info: Found entity 1: tshftrg
Info: Found 2 design units, including 1 entities, in source file TX_STSRG.VHD
    Info: Found design unit 1: tx_stsrg-rtl
    Info: Found entity 1: tx_stsrg
Info: Found 2 design units, including 1 entities, in source file TXCLKCNT.VHD
    Info: Found design unit 1: txclkcnt-rtl
    Info: Found entity 1: txclkcnt
Info: Found 2 design units, including 1 entities, in source file XMIT_REG.VHD
    Info: Found design unit 1: xmit_reg-rtl
    Info: Found entity 1: xmit_reg
Info: Found 2 design units, including 1 entities, in source file A6850.vhd
    Info: Found design unit 1: a6850-struct
    Info: Found entity 1: a6850
Info: Elaborating entity "A6850" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at A6850.vhd(65): object "ws2" declared but not used
Info: Elaborating entity "rxcntl" for hierarchy "rxcntl:u1"
Info: Elaborating entity "rxcntlsm" for hierarchy "rxcntl:u1|rxcntlsm:u1"
Info: Elaborating entity "datcount" for hierarchy "rxcntl:u1|datcount:u2"
Info: (10035) Verilog HDL or VHDL information at DATCOUNT.VHD(61): object "int_tc2" declared but not used
Info: Elaborating entity "rxcount" for hierarchy "rxcntl:u1|rxcount:u3"
Info: Elaborating entity "framerr" for hierarchy "rxcntl:u1|framerr:u4"
Info: Elaborating entity "par_tree" for hierarchy "par_tree:u2"
Info: Elaborating entity "rcv_reg" for hierarchy "rcv_reg:u3"
Info: Elaborating entity "stsrg" for hierarchy "stsrg:u4"
Info: Elaborating entity "tx_stsrg" for hierarchy "stsrg:u4|tx_stsrg:u1"
Info: Elaborating entity "rx_stsrg" for hierarchy "stsrg:u4|rx_stsrg:u2"
Warning: Verilog HDL or VHDL warning at RX_STSRG.VHD(215): duplicated signal using variable int_dout found in event expression.
Warning: Verilog HDL or VHDL warning at RX_STSRG.VHD(216): duplicated signal using variable int_dout found in event expression.
Info: Elaborating entity "rxshftrg" for hierarchy "rxshftrg:u5"
Info: Elaborating entity "cntl_reg" for hierarchy "cntl_reg:u6"
Info: Elaborating entity "bus_cntl" for hierarchy "bus_cntl:u7"
Info: Elaborating entity "tcntl" for hierarchy "tcntl:u8"
Info: Elaborating entity "transm" for hierarchy "tcntl:u8|transm:u1"
Info: VHDL Case Statement information at TRANSM.VHD(287): OTHERS choice is never selected
Info: Elaborating entity "datacnt" for hierarchy "tcntl:u8|datacnt:u2"
Info: Elaborating entity "txclkcnt" for hierarchy "tcntl:u8|txclkcnt:u3"
Info: Elaborating entity "srpargen" for hierarchy "srpargen:u9"
Info: Elaborating entity "datamux" for hierarchy "srpargen:u9|datamux:u1"
Info: Elaborating entity "pargen" for hierarchy "srpargen:u9|pargen:u2"
Info: Elaborating entity "tshftrg" for hierarchy "srpargen:u9|tshftrg:u3"
Info: Elaborating entity "mux" for hierarchy "srpargen:u9|mux:u4"
Info: Elaborating entity "brkmux" for hierarchy "srpargen:u9|brkmux:u5"
Info: Elaborating entity "xmit_reg" for hierarchy "xmit_reg:u10"
Info: State machine "|a6850|tcntl:u8|transm:u1|state" contains 6 states and 0 state bits
Info: State machine "|a6850|rxcntl:u1|rxcntlsm:u1|state" contains 15 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|a6850|tcntl:u8|transm:u1|state"
Info: Encoding result for state machine "|a6850|tcntl:u8|transm:u1|state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "tcntl:u8|transm:u1|state.stop2"
        Info: Encoded state bit "tcntl:u8|transm:u1|state.stop1"
        Info: Encoded state bit "tcntl:u8|transm:u1|state.parity"
        Info: Encoded state bit "tcntl:u8|transm:u1|state.data"
        Info: Encoded state bit "tcntl:u8|transm:u1|state.start"
        Info: Encoded state bit "tcntl:u8|transm:u1|state.ini"
    Info: State "|a6850|tcntl:u8|transm:u1|state.ini" uses code string "000000"
    Info: State "|a6850|tcntl:u8|transm:u1|state.start" uses code string "000011"
    Info: State "|a6850|tcntl:u8|transm:u1|state.data" uses code string "000101"
    Info: State "|a6850|tcntl:u8|transm:u1|state.parity" uses code string "001001"
    Info: State "|a6850|tcntl:u8|transm:u1|state.stop1" uses code string "010001"
    Info: State "|a6850|tcntl:u8|transm:u1|state.stop2" uses code string "100001"
Info: Selected Auto state machine encoding method for state machine "|a6850|rxcntl:u1|rxcntlsm:u1|state"
Info: Encoding result for state machine "|a6850|rxcntl:u1|rxcntlsm:u1|state"
    Info: Completed encoding using 15 state bits
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.overrun"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.db1_stop2"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.db1_stop1"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.db1_parity"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.db1_data"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.sample_stop2"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.wait_stop2"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.sample_stop1"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.wait_stop1"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.sample_parity"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.wait_parity"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.sample_data"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.wait_data"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.synch"
        Info: Encoded state bit "rxcntl:u1|rxcntlsm:u1|state.wait_start"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.wait_start" uses code string "000000000000000"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.synch" uses code string "000000000000011"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.wait_data" uses code string "000000000000101"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.sample_data" uses code string "000000000001001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.wait_parity" uses code string "000000000010001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.sample_parity" uses code string "000000000100001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.wait_stop1" uses code string "000000001000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.sample_stop1" uses code string "000000010000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.wait_stop2" uses code string "000000100000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.sample_stop2" uses code string "000001000000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.db1_data" uses code string "000010000000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.db1_parity" uses code string "000100000000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.db1_stop1" uses code string "001000000000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.db1_stop2" uses code string "010000000000001"
    Info: State "|a6850|rxcntl:u1|rxcntlsm:u1|state.overrun" uses code string "100000000000001"
Info: Registers with preset signals will power-up high
Info: Implemented 240 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 11 output pins
    Info: Implemented 209 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Fri Dec 23 19:42:13 2005
    Info: Elapsed time: 00:00:23