a6850.quartus

来自「本文件是altera公司fpga的ip核」· QUARTUS 代码 · 共 42 行

FILES
{
	VHDL_FILE = BRKMUX.VHD;
	VHDL_FILE = BUS_CNTL.VHD;
	VHDL_FILE = CNTL_REG.VHD;
	VHDL_FILE = DATACNT.VHD;
	VHDL_FILE = DATAMUX.VHD;
	VHDL_FILE = DATCOUNT.VHD;
	VHDL_FILE = FRAMERR.VHD;
	VHDL_FILE = MUX.VHD;
	VHDL_FILE = PAR_TREE.VHD;
	VHDL_FILE = PARGEN.VHD;
	VHDL_FILE = RCV_REG.VHD;
	VHDL_FILE = RX_STSRG.VHD;
	VHDL_FILE = RXCNTL.VHD;
	VHDL_FILE = RXCNTLSM.VHD;
	VHDL_FILE = RXCOUNT.VHD;
	VHDL_FILE = RXSHFTRG.VHD;
	VHDL_FILE = SRPARGEN.VHD;
	VHDL_FILE = STSRG.VHD;
	VHDL_FILE = TCNTL.VHD;
	VHDL_FILE = TRANSM.VHD;
	VHDL_FILE = TSHFTRG.VHD;
	VHDL_FILE = TX_STSRG.VHD;
	VHDL_FILE = TXCLKCNT.VHD;
	VHDL_FILE = XMIT_REG.VHD;
	VHDL_FILE = A6850.vhd;
}
COMPILER_SETTINGS_LIST
{
	COMPILER_SETTINGS = A6850;
}
SIMULATOR_SETTINGS_LIST
{
	SIMULATOR_SETTINGS = A6850;
}
SOFTWARE_SETTINGS_LIST
{
	SOFTWARE_SETTINGS = Debug;
	SOFTWARE_SETTINGS = Release;
}