a6850.psf

本文件是altera公司fpga的ip核

EDA_TOOL_SETTINGS(eda_palace)
{
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
	COMPILE_USING_RESYNTHESIS = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
}
EDA_TOOL_SETTINGS(eda_board_design)
{
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
	COMPILE_USING_RESYNTHESIS = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
}
EDA_TOOL_SETTINGS(eda_simulation)
{
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
	COMPILE_USING_RESYNTHESIS = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
}
EDA_TOOL_SETTINGS(eda_design_synthesis)
{
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
	COMPILE_USING_RESYNTHESIS = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDA_INPUT_DATA_FORMAT = EDIF;
	EDA_INPUT_VCC_NAME = VCC;
	EDA_INPUT_GND_NAME = GND;
}
EDA_TOOL_SETTINGS(eda_timing_analysis)
{
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
	COMPILE_USING_RESYNTHESIS = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
}
EDA_TOOL_SETTINGS(eda_formal_verification)
{
	USE_GENERATED_PHYSICAL_CONSTRAINTS = ON;
	RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL;
	RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL;
	RESYNTHESIS_RETIMING = FULL;
	COMPILE_USING_RESYNTHESIS = OFF;
	EDA_OUTPUT_DATA_FORMAT = NONE;
	EDA_RUN_TOOL_AUTOMATICALLY = OFF;
	EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF;
	EDA_MAP_ILLEGAL_CHARACTERS = OFF;
	EDA_FLATTEN_BUSES = OFF;
	EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF;
	EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF;
}
HDL_SETTINGS
{
	VERILOG_INPUT_VERSION = VERILOG_2001;
}
DEFAULT_TIMING_REQUIREMENTS
{
	INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF;
	RUN_ALL_TIMING_ANALYSES = OFF;
	IGNORE_CLOCK_SETTINGS = OFF;
	DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE";
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_READ_DURING_WRITE_PATHS = ON;
	CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON;
	NUMBER_OF_PATHS_TO_REPORT = 200;
	NUMBER_OF_DESTINATION_TO_REPORT = 10;
	NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10;
	MAX_SCC_SIZE = 50;
}
DEFAULT_HARDCOPY_SETTINGS
{
	HCPY_GEN_FILES_DURING_COMPILATION = OFF;
	HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 ns";
	HARDCOPY_MINIMUM_REQUIRED_TPD = "0.0 ns";
	HARDCOPY_MINIMUM_REQUIRED_TCO = "0.0 ns";
}
SYNTHESIS_FITTING_SETTINGS
{
	AUTO_SHIFT_REGISTER_RECOGNITION = ON;
	AUTO_DSP_RECOGNITION = ON;
	AUTO_RAM_RECOGNITION = ON;
	REMOVE_DUPLICATE_LOGIC = ON;
	AUTO_TURBO_BIT = ON;
	AUTO_MERGE_PLLS = ON;
	AUTO_OPEN_DRAIN_PINS = ON;
	AUTO_PARALLEL_EXPANDERS = ON;
	AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF;
	AUTO_FAST_OUTPUT_REGISTERS = OFF;
	AUTO_FAST_INPUT_REGISTERS = OFF;
	AUTO_CASCADE_CHAINS = ON;
	AUTO_CARRY_CHAINS = ON;
	AUTO_DELAY_CHAINS = ON;
	MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4;
	PARALLEL_EXPANDER_CHAIN_LENGTH = 16;
	CASCADE_CHAIN_LENGTH = 2;
	STRATIX_CARRY_CHAIN_LENGTH = 70;
	MERCURY_CARRY_CHAIN_LENGTH = 48;
	FLEX10K_CARRY_CHAIN_LENGTH = 32;
	FLEX6K_CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN_LENGTH = 48;
	AUTO_LCELL_INSERTION = ON;
	ALLOW_XOR_GATE_USAGE = ON;
	AUTO_MODIFIED_PACKED_REGISTERS = NORMAL;
	AUTO_PACKED_REGISTERS = OFF;
	FLEX10K_OPTIMIZATION_TECHNIQUE = AREA;
	FLEX6K_OPTIMIZATION_TECHNIQUE = AREA;
	MERCURY_OPTIMIZATION_TECHNIQUE = AREA;
	APEX20K_OPTIMIZATION_TECHNIQUE = SPEED;
	MAX7000_OPTIMIZATION_TECHNIQUE = AREA;
	STRATIX_OPTIMIZATION_TECHNIQUE = SPEED;
	FLEX10K_TECHNOLOGY_MAPPER = LUT;
	FLEX6K_TECHNOLOGY_MAPPER = LUT;
	MERCURY_TECHNOLOGY_MAPPER = LUT;
	APEX20K_TECHNOLOGY_MAPPER = LUT;
	MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM";
	STRATIX_TECHNOLOGY_MAPPER = LUT;
	AUTO_IMPLEMENT_IN_ROM = OFF;
	AUTO_GLOBAL_MEMORY_CONTROLS = OFF;
	AUTO_GLOBAL_REGISTER_CONTROLS = ON;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_CLOCK = ON;
	USE_LPM_FOR_AHDL_OPERATORS = ON;
	LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF;
	ENABLE_BUS_HOLD_CIRCUITRY = OFF;
	WEAK_PULL_UP_RESISTOR = OFF;
	TURBO_BIT = ON;
	MAX7000_IGNORE_SOFT_BUFFERS = OFF;
	IGNORE_SOFT_BUFFERS = ON;
	IGNORE_LCELL_BUFFERS = OFF;
	IGNORE_ROW_GLOBAL_BUFFERS = OFF;
	IGNORE_GLOBAL_BUFFERS = OFF;
	IGNORE_CASCADE_BUFFERS = OFF;
	IGNORE_CARRY_BUFFERS = OFF;
	REMOVE_DUPLICATE_REGISTERS = ON;
	REMOVE_REDUNDANT_LOGIC_CELLS = OFF;
	ALLOW_POWER_UP_DONT_CARE = ON;
	PCI_IO = OFF;
	NOT_GATE_PUSH_BACK = ON;
	SLOW_SLEW_RATE = OFF;
	DSP_BLOCK_BALANCING = AUTO;
	STATE_MACHINE_PROCESSING = AUTO;
}
THIRD_PARTY_EDA_TOOLS(A6850)
{
	EDA_RESYNTHESIS_TOOL = "<NONE>";
	EDA_FORMAL_VERIFICATION_TOOL = "<NONE>";
	EDA_BOARD_DESIGN_TOOL = "<NONE>";
	EDA_TIMING_ANALYSIS_TOOL = "<NONE>";
	EDA_SIMULATION_TOOL = "<NONE>";
	EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>";
}