d_bcd.syr

CPLD制作的BCD译码器软件,包含源代码等

Release 5.2i - xst F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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--> Reading design: d_bcd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Low Level Synthesis
  6) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : d_bcd.prj
Input Format                       : VHDL
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : d_bcd
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Entity Name                        : d_bcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : lower

---- Other Options
cross_clock_analysis               : NO
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/D_BCD is now defined in a different file: was F:/CPLD_BOARD/d_BCD/d_BCD.vhd, now is E:/FHAL/CPLD/d_BCD/d_BCD.vhd
WARNING:HDLParsers:3215 - Unit work/D_BCD/BEHAVIORAL is now defined in a different file: was F:/CPLD_BOARD/d_BCD/d_BCD.vhd, now is E:/FHAL/CPLD/d_BCD/d_BCD.vhd
Compiling vhdl file E:/FHAL/CPLD/d_BCD/d_BCD.vhd in Library work.
Architecture behavioral of Entity d_bcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <d_bcd> (Architecture <behavioral>).
Entity <d_bcd> analyzed. Unit <d_bcd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <d_bcd>.
    Related source file is E:/FHAL/CPLD/d_BCD/d_BCD.vhd.
    Found 16x7-bit ROM for signal <$n0000> created at line 24.
    Summary:
	inferred   1 ROM(s).
Unit <d_bcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x7-bit ROM                     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx/xc9500xl/data/lib.xst" Consulted
Library "D:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <d_bcd> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : d_bcd.ngr
Top Level Output File Name         : d_bcd
Output Format                      : NGC
Optimization Criterion             : Speed
Keep Hierarchy                     : YES
Macro Generator                    : macro+
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 26

Cell Usage :
# BELS                             : 73
#      AND2                        : 24
#      AND3                        : 3
#      INV                         : 20
#      OR2                         : 23
#      OR3                         : 3
# IO Buffers                       : 26
#      IBUF                        : 5
#      OBUF                        : 21
=========================================================================
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Total memory usage is 45520 kilobytes