plslat.edn

CPLD制作的BCD译码器软件,包含源代码等

(edif plslat
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
     (timeStamp 1999 12 09 09 52 15)
     (program "XST EDIF NetWriter")
    )
   )
  (Library DESIGNS
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDCP (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT))
           (port CLR (direction INPUT))
           (port PRE (direction INPUT))
         )
       )
    )
    (cell AND2 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
    (cell plslat (cellType GENERIC)
       (view behavior (viewType NETLIST)
         (interface
           (port G (direction INPUT))
           (port D (direction INPUT))
           (port Q (direction OUTPUT))
         )
         (contents
          (instance I_GND (viewRef netlist (cellRef GND (libraryRef DESIGNS)))          )
          (instance I_1_INV (viewRef netlist (cellRef INV (libraryRef DESIGNS)))          )
          (instance I_2_INV (viewRef netlist (cellRef INV (libraryRef DESIGNS)))          )
          (instance I_FDCP (viewRef netlist (cellRef FDCP (libraryRef DESIGNS)))          )
          (instance I_1_AND2 (viewRef netlist (cellRef AND2 (libraryRef DESIGNS)))          )
          (instance I_2_AND2 (viewRef netlist (cellRef AND2 (libraryRef DESIGNS)))          )
          (net GND (joined
           (portRef C (instanceRef I_FDCP))
           (portRef D (instanceRef I_FDCP))
           (portRef G (instanceRef I_GND))
          ))
          (net I_2_INV (joined
           (portRef I1 (instanceRef I_2_AND2))
           (portRef I1 (instanceRef I_1_AND2))
           (portRef O (instanceRef I_2_INV))
          ))
          (net N101 (joined
           (portRef O (instanceRef I_2_AND2))
           (portRef CLR (instanceRef I_FDCP))
          ))
          (net N102 (joined
           (portRef O (instanceRef I_1_AND2))
           (portRef PRE (instanceRef I_FDCP))
          ))
          (net I_1_INV (joined
           (portRef I0 (instanceRef I_2_AND2))
           (portRef O (instanceRef I_1_INV))
          ))
          (net G (joined
           (portRef I (instanceRef I_2_INV))
           (portRef G)
          ))
          (net D (joined
           (portRef I0 (instanceRef I_1_AND2))
           (portRef I (instanceRef I_1_INV))
           (portRef D)
          ))
          (net Q (joined
           (portRef Q (instanceRef I_FDCP))
           (portRef Q)
          ))
         )
       )
    )
  )
  (design PCB
    (cellref plslat (libraryref DESIGNS))
  )
)