__projnav.log

CPLD制作的BCD译码器软件,包含源代码等

ISE Auto-Make Log File
-----------------------

Updating: Configure Device (iMPACT)

Launching: 'impact -f __impact.rsp'



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    d_BCD.vhd
Scanning    d_BCD.vhd
Writing d_BCD.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/D_BCD is now defined in a different file: was F:/CPLD_BOARD/d_BCD/d_BCD.vhd, now is E:/FHAL/CPLD/d_BCD/d_BCD.vhd
WARNING:HDLParsers:3215 - Unit work/D_BCD/BEHAVIORAL is now defined in a different file: was F:/CPLD_BOARD/d_BCD/d_BCD.vhd, now is E:/FHAL/CPLD/d_BCD/d_BCD.vhd
Compiling vhdl file E:/FHAL/CPLD/d_BCD/d_BCD.vhd in Library work.
Architecture behavioral of Entity d_bcd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <d_bcd> (Architecture <behavioral>).
Entity <d_bcd> analyzed. Unit <d_bcd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <d_bcd>.
    Related source file is E:/FHAL/CPLD/d_BCD/d_BCD.vhd.
    Found 16x7-bit ROM for signal <$n0000> created at line 24.
    Summary:
	inferred   1 ROM(s).
Unit <d_bcd> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x7-bit ROM                     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx/xc9500xl/data/lib.xst" Consulted
Library "D:/Xilinx/data/librtl.xst" Consulted

Optimizing unit <d_bcd> ...

Completed process "Synthesize".



Started process "Translate".

Release 5.2i - ngdbuild F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -i -p xc9500xl d_bcd.ngc d_bcd.ngd 

Reading NGO file "E:/FHAL/CPLD/d_BCD/d_bcd.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "d_bcd.ngd" ...

Writing NGDBUILD log file "d_bcd.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Fit".

Release 5.2i - CPLD Optimizer/Partitioner F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Considering device XC95144XL-TQ100.
Flattening design..
Timing optimization
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 21 equations into 8 function blocks...........................

Design d_bcd has been optimized and fit into device XC95144XL-5-TQ100.

Completed process "Fit".


Started process "Generate Timing".

Release 5.2i - Timing Report Generator F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Path tracing .....
The number of paths traced: 105.

Generating performance summary ...
d_bcd.tim has been created.

Generating Stamp model files d_bcd.mod, d_bcd.data ...
d_bcd.mod has been created.
d_bcd.data has been created.

Completed process "Generate Timing".



Started process "Generate Programming File".

Release 5.2i - Programming File Generator F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Programming File".

Release 5.2i - Programming File Generator F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Programming File".

Release 5.2i - Programming File Generator F.28
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------