main_bcd.vhd

来自「CPLD制作的BCD译码器软件,包含源代码等」· VHDL 代码 · 共 41 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main_bcd is
    Port (cs_sw8								:in std_logic;
  	  	    p_sw1,p_sw2,p_sw3,p_sw4	   :in std_logic;
		    LED1_out							:out std_logic_vector(6 downto 0);
		    LED2_out							:out std_logic_vector(6 downto 0);
		    LED3_out							:out std_logic_vector(6 downto 0)
 			 );
end main_bcd;

architecture Behavioral of main_bcd is
   component    d_bcd
     port(cs_sw8								:in std_logic;
  		    p_sw1,p_sw2,p_sw3,p_sw4	   :in std_logic;
		    LED1_out							:out std_logic_vector(6 downto 0);
		    LED2_out							:out std_logic_vector(6 downto 0);
		    LED3_out							:out std_logic_vector(6 downto 0)
 			 );
     end component;
 
begin
 l0:d_bcd
 
     port map
        ( cs_sw8		=>cs_sw8,														
  	  	    p_sw1		=>p_sw1,
  	  	    p_sw2		=>p_sw2,
  	  	    p_sw3		=>p_sw3,
  	  	    p_sw4		=>p_sw4,
		    LED1_out   =>LED1_out,							
		    LED2_out   =>LED2_out,							
		    LED3_out   =>LED2_out							
        );
   
  
end Behavioral;