d_bcd.tim

来自「CPLD制作的BCD译码器软件,包含源代码等」· TIM 代码 · 共 83 行

                           Performance Summary Report
                           --------------------------

Design:     d_bcd
Device:     XC95144XL-5-TQ100
Speed File: Version 3.0
Program:    Timing Report Generator:  version F.28
Date:       Mon Jul 11 16:57:54 2005

Performance Summary:

Pad to Pad (tPD)                          :          5.0ns (1 macrocell levels)
Pad 'cs_sw8' to Pad 'led1_out<1>'                                 

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From          c     p     p     p     p
 \              s     _     _     _     _
  \             _     s     s     s     s
   \            s     w     w     w     w
    \           w     1     2     3     4
     \          8                        
      \                                  
       \                                 
        \                                
         \                               
          \                              
  To       \------------------------------

led1_out<0>   5.0   5.0   5.0   5.0   5.0
led1_out<1>   5.0   5.0   5.0   5.0   5.0
led1_out<2>   5.0   5.0   5.0   5.0   5.0
led1_out<3>   5.0   5.0   5.0   5.0   5.0
led1_out<4>   5.0   5.0   5.0   5.0   5.0
led1_out<5>   5.0   5.0   5.0   5.0   5.0
led1_out<6>   5.0   5.0   5.0   5.0   5.0
led2_out<0>   5.0   5.0   5.0   5.0   5.0
led2_out<1>   5.0   5.0   5.0   5.0   5.0
led2_out<2>   5.0   5.0   5.0   5.0   5.0
led2_out<3>   5.0   5.0   5.0   5.0   5.0
led2_out<4>   5.0   5.0   5.0   5.0   5.0
led2_out<5>   5.0   5.0   5.0   5.0   5.0
led2_out<6>   5.0   5.0   5.0   5.0   5.0
led3_out<0>   5.0   5.0   5.0   5.0   5.0
led3_out<1>   5.0   5.0   5.0   5.0   5.0
led3_out<2>   5.0   5.0   5.0   5.0   5.0
led3_out<3>   5.0   5.0   5.0   5.0   5.0
led3_out<4>   5.0   5.0   5.0   5.0   5.0
led3_out<5>   5.0   5.0   5.0   5.0   5.0
led3_out<6>   5.0   5.0   5.0   5.0   5.0

Path Type Definition: 

Pad to Pad (tPD) -                        Reports pad to pad paths that start 
                                          at input pads and end at output pads. 
                                          Paths are not traced through 
                                          registers. 

Clock Pad to Output Pad (tCO) -           Reports paths that start at input 
                                          pads trace through clock inputs of 
                                          registers and end at output pads. 
                                          Paths are not traced through PRE/CLR 
                                          inputs of registers. 

Setup to Clock at Pad (tSU or tSUF) -     Reports external setup time of data 
                                          to clock at pad. Data path starts at 
                                          an input pad and ends at register 
                                          (Fast Input Register for tSUF) D/T 
                                          input. Clock path starts at input pad 
                                          and ends at the register clock input. 
                                          Paths are not traced through 
                                          registers. Pin-to-pin setup 
                                          requirement is not reported or 
                                          guaranteed for product-term clocks 
                                          derived from macrocell feedback 
                                          signals. 

Clock to Setup (tCYC) -                   Register to register cycle time. 
                                          Include source register tCO and 
                                          destination register tSU.