📄 d_bcd.rpt
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cpldfit: version F.28 Xilinx Inc.
Fitter Report
Design Name: d_bcd Date: 7-11-2005, 4:57PM
Device Used: XC95144XL-5-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
21 /144 ( 15%) 78 /720 ( 11%) 0 /144 ( 0%) 26 /81 ( 32%) 40 /432 ( 9%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 5 5 | I/O : 26 47
Output : 21 21 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 26 26
MACROCELL RESOURCES:
Total Macrocells Available 144
Registered Macrocells 0
Non-registered Macrocell driving I/O 21
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 21 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 21 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
led1_out<0> 4 5 FB3_5 STD FAST 24 I/O O
led1_out<1> 4 5 FB3_11 STD FAST 29 I/O O
led1_out<2> 3 5 FB3_15 STD FAST 33 I/O O
led1_out<3> 5 5 FB6_5 STD FAST 76 I/O O
led1_out<4> 2 5 FB2_11 STD FAST 6 I/O O
led1_out<5> 4 5 FB1_6 STD FAST 14 I/O O
led1_out<6> 4 5 FB6_11 STD FAST 80 I/O O
led2_out<0> 4 5 FB5_2 STD FAST 35 I/O O
led2_out<1> 4 5 FB5_8 STD FAST 39 I/O O
led2_out<2> 3 5 FB5_12 STD FAST 42 I/O O
led2_out<3> 5 5 FB8_5 STD FAST 64 I/O O
led2_out<4> 2 5 FB2_14 STD FAST 8 I/O O
led2_out<5> 4 5 FB1_11 STD FAST 17 I/O O
led2_out<6> 4 5 FB8_11 STD FAST 68 I/O O
led3_out<0> 4 5 FB7_11 STD FAST 56 I/O O
led3_out<1> 4 5 FB1_2 STD FAST 11 I/O O
led3_out<2> 3 5 FB4_12 STD FAST 94 I/O O
led3_out<3> 5 5 FB7_5 STD FAST 52 I/O O
led3_out<4> 2 5 FB2_17 STD FAST 10 I/O O
led3_out<5> 4 5 FB4_2 STD FAST 87 I/O O
led3_out<6> 4 5 FB4_8 STD FAST 91 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
cs_sw8 FB4_9 92 I/O I
p_sw1 FB6_6 77 I/O I
p_sw2 FB4_15 96 I/O I
p_sw3 FB2_12 7 I/O I
p_sw4 FB3_6 25 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 3 5 5 12 3/0 11
FB2 3 5 5 6 3/0 10
FB3 3 5 5 11 3/0 10
FB4 3 5 5 11 3/0 10
FB5 3 5 5 11 3/0 10
FB6 2 5 5 9 2/0 10
FB7 2 5 5 9 2/0 10
FB8 2 5 5 9 2/0 10
---- ----- ----- -----
21 78 21/0 81
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/49
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
led3_out<1> 4 0 0 1 FB1_2 STD 11 I/O O
(unused) 0 0 0 5 FB1_3 12 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 13 I/O
led1_out<5> 4 0 0 1 FB1_6 STD 14 I/O O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 15 I/O
(unused) 0 0 0 5 FB1_9 16 I/O
(unused) 0 0 0 5 FB1_10 (b)
led2_out<5> 4 0 0 1 FB1_11 STD 17 I/O O
(unused) 0 0 0 5 FB1_12 18 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 19 I/O
(unused) 0 0 0 5 FB1_15 20 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 22 GCK/I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: cs_sw8 3: p_sw2 5: p_sw4
2: p_sw1 4: p_sw3
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
led3_out<1> XXXXX................................... 5 5
led1_out<5> XXXXX................................... 5 5
led2_out<5> XXXXX................................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 5/49
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 99 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 1 GTS/I/O
(unused) 0 0 0 5 FB2_6 2 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 3 GTS/I/O
(unused) 0 0 0 5 FB2_9 4 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
led1_out<4> 2 0 0 3 FB2_11 STD 6 I/O O
(unused) 0 0 0 5 FB2_12 7 I/O I
(unused) 0 0 0 5 FB2_13 (b)
led2_out<4> 2 0 0 3 FB2_14 STD 8 I/O O
(unused) 0 0 0 5 FB2_15 9 I/O
(unused) 0 0 0 5 FB2_16 (b)
led3_out<4> 2 0 0 3 FB2_17 STD 10 I/O O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: cs_sw8 3: p_sw2 5: p_sw4
2: p_sw1 4: p_sw3
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
led1_out<4> XXXXX................................... 5 5
led2_out<4> XXXXX................................... 5 5
led3_out<4> XXXXX................................... 5 5
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 5/49
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 23 GCK/I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
led1_out<0> 4 0 0 1 FB3_5 STD 24 I/O O
(unused) 0 0 0 5 FB3_6 25 I/O I
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 27 GCK/I/O
(unused) 0 0 0 5 FB3_9 28 I/O
(unused) 0 0 0 5 FB3_10 (b)
led1_out<1> 4 0 0 1 FB3_11 STD 29 I/O O
(unused) 0 0 0 5 FB3_12 30 I/O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 32 I/O
led1_out<2> 3 0 0 2 FB3_15 STD 33 I/O O
(unused) 0 0 0 5 FB3_16 (b)
(unused) 0 0 0 5 FB3_17 34 I/O
(unused) 0 0 0 5 FB3_18 (b)
Signals Used by Logic in Function Block
1: cs_sw8 3: p_sw2 5: p_sw4
2: p_sw1 4: p_sw3
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
led1_out<0> XXXXX................................... 5 5
led1_out<1> XXXXX................................... 5 5
led1_out<2> XXXXX................................... 5 5
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