main_bcd.syr

CPLD制作的BCD译码器软件,包含源代码等

Release 4.1WP1.x - xst E.31
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
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--> Parameter overwrite set to YES
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--> Parameter xsthdpdir set to ./xst
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--> =========================================================================
---- Source Parameters
Input Format                       : VHDL
Input File Name                    : main_bcd.prj

---- Target Parameters
Target Device                      : XC9500XL
Output File Name                   : main_bcd
Output Format                      : NGC
Target Technology                  : 9500xl

---- Source Options
Entity Name                        : main_bcd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================

Compiling vhdl file F:/CPLD_BOARD/d_BCD/d_BCD.vhd in Library work.
Entity <d_bcd> (Architecture <behavioral>) compiled.
Compiling vhdl file F:/CPLD_BOARD/d_BCD/main_bcd.vhd in Library work.
Entity <main_bcd> (Architecture <behavioral>) compiled.

Analyzing Entity <main_bcd> (Architecture <Behavioral>).
Entity <main_bcd> analyzed. Unit <main_bcd> generated.

Analyzing Entity <d_bcd> (Architecture <behavioral>).
Entity <d_bcd> analyzed. Unit <d_bcd> generated.


Synthesizing Unit <d_bcd>.
    Related source file is F:/CPLD_BOARD/d_BCD/d_BCD.vhd.
    Found 16x7-bit ROM for internal node.
    Summary:
	inferred   1 ROM(s).
Unit <d_bcd> synthesized.


Synthesizing Unit <main_bcd>.
    Related source file is F:/CPLD_BOARD/d_BCD/main_bcd.vhd.
WARNING:Xst:644 - Signal <led2_out<5>> has a multisource.
WARNING:Xst:644 - Signal <led2_out<4>> has a multisource.
WARNING:Xst:644 - Signal <led2_out<3>> has a multisource.
WARNING:Xst:644 - Signal <led2_out<2>> has a multisource.
WARNING:Xst:644 - Signal <led2_out<1>> has a multisource.
WARNING:Xst:644 - Signal <led2_out<0>> has a multisource.
WARNING:Xst:644 - Signal <led2_out<6>> has a multisource.
WARNING:Xst:648 -  Output <led3_out<6>> is never used.
WARNING:Xst:648 -  Output <led3_out<5>> is never used.
WARNING:Xst:648 -  Output <led3_out<4>> is never used.
WARNING:Xst:648 -  Output <led3_out<3>> is never used.
WARNING:Xst:648 -  Output <led3_out<2>> is never used.
WARNING:Xst:648 -  Output <led3_out<1>> is never used.
WARNING:Xst:648 -  Output <led3_out<0>> is never used.
Unit <main_bcd> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x7-bit ROM                     : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <d_bcd> ...

Optimizing unit <main_bcd> ...

Merging netlists...

=========================================================================
Final Results
Output File Name                   : main_bcd
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500xl
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Design Statistics
# Edif Instances                   : 125
# I/Os                             : 26

=========================================================================
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