freqtest.vhd

来自「可编程逻辑设计的程序！24位十进制频率计！可使ＥＤＡ实验年箱测量指定频率！」· VHDL 代码 · 共 42 行

LIBRARY IEEE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FREQTEST IS
   PORT (CLK1HZ:IN STD_LOGIC;
         FSIN: IN STD_LOGIC;
         SHOW:OUT STD_LOGIC;
         DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END FREQTEST;
ARCHITECTURE struc OF FREQTEST IS
COMPONENT FTCTRL
     PORT(CLKK: IN STD_LOGIC;
        CNT_EN: OUT STD_LOGIC;
        RST_CNT: OUT STD_LOGIC;
        Load:     OUT STD_LOGIC);
  END COMPONENT;
COMPONENT COUNTER24B
     PORT(FIN: IN STD_LOGIC;
        CLR: IN STD_LOGIC;
        ENABL: IN STD_LOGIC;
        COUT:OUT STD_LOGIC;
        DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
  END COMPONENT;
COMPONENT REG24B
    PORT(LK: IN STD_LOGIC;
         DIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);
         DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
  END COMPONENT;
SIGNAL TSTEN1:STD_LOGIC;
SIGNAL CLR_CNT1:STD_LOGIC;
SIGNAL Load1:STD_LOGIC;
SIGNAL DTO1:STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL CARRY_OUT1:STD_LOGIC_VECTOR(5 DOWNTO 0);
 BEGIN
   U1: FTCTRL PORT MAP (CLKK=>CLK1HZ,CNT_EN=>TSTEN1,RST_CNT=>CLR_CNT1,Load=>Load1);
   U2:REG24B PORT MAP (LK=>Load1,DIN=>DTO1,DOUT=>DOUT);
   U3: COUNTER24B PORT MAP (FIN=>FSIN,CLR=>CLR_CNT1,ENABL=>TSTEN1,DOUT=>DTO1,COUT=>SHOW);
END struc;