reg24b.vhd

来自「可编程逻辑设计的程序！24位十进制频率计！可使ＥＤＡ实验年箱测量指定频率！」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG24B IS
   PORT(LK: IN STD_LOGIC;
         DIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);
         DOUT:OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END REG24B ;
ARCHITECTURE behav OF REG24B IS
BEGIN
  PROCESS(LK,DIN)
    BEGIN
    IF LK'EVENT AND LK='1' THEN DOUT<=DIN;
    END IF;
  END PROCESS;
END behav;