📄 control_mem_rtl.vhd
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-------------------------------------------------------------------------------
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-- Web: http://www.oregano.at/ --
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-- Contact: 8051@oregano.at --
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-------------------------------------------------------------------------------
-- --
-- MC8051 - VHDL 8051 Microcontroller IP Core --
-- Copyright (C) 2001 OREGANO SYSTEMS --
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file LGPL.TXT. --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
--
--
-- Author: Helmut Mayrhofer
--
-- Filename: control_mem_rtl.vhd
--
-- Date of Creation: Mon Aug 9 12:14:48 1999
--
-- Version: $Revision: 1.10 $
--
-- Date of Latest Version: $Date: 2006/09/07 10:01:10 $
--
--
-- Description: Describe all sequential funcitonality like read from
-- special function registers, observe interrupt sources,
-- write to special function registers, and read or write
-- to the bit addressable memory area.
--
--
--
--
-------------------------------------------------------------------------------
architecture rtl of control_mem is
type t_gprbit is array (15 downto 0) of unsigned(7 downto 0);
subtype muxint is integer range C_IMPL_N_TMR-1 downto 0;
signal s_help: unsigned (7 downto 0); -- general help-register
signal s_help16: unsigned (15 downto 0); -- 16 bit help-register
signal s_helpb : std_logic; -- general help-bit
signal s_ir: unsigned (7 downto 0); -- reg for saving the command
signal gprbit: t_gprbit; -- bitadressable general purpose RAM
signal s_r0_b0: unsigned (7 downto 0); -- Register R0 / Bank 0
signal s_r1_b0: unsigned (7 downto 0); -- Register R1 / Bank 0
signal s_r0_b1: unsigned (7 downto 0); -- Register R0 / Bank 1
signal s_r1_b1: unsigned (7 downto 0); -- Register R1 / Bank 1
signal s_r0_b2: unsigned (7 downto 0); -- Register R0 / Bank 2
signal s_r1_b2: unsigned (7 downto 0); -- Register R1 / Bank 2
signal s_r0_b3: unsigned (7 downto 0); -- Register R0 / Bank 3
signal s_r1_b3: unsigned (7 downto 0); -- Register R1 / Bank 3
signal s_reg_data: unsigned (7 downto 0); -- equals reg_data_o
Signal state: t_state; -- actual state
signal s_command: std_logic_vector (7 downto 0);
signal s_pc_inc_en : std_logic_vector (3 downto 0);
signal s_regs_wr_en : std_logic_vector (2 downto 0);
signal s_data_mux : std_logic_vector (3 downto 0);
signal s_bdata_mux : std_logic_vector (3 downto 0);
signal s_adr_mux : std_logic_vector (3 downto 0);
signal s_adrx_mux : std_logic_vector (1 downto 0);
signal s_help_en : std_logic_vector (3 downto 0);
signal s_help16_en : std_logic_vector (1 downto 0);
signal s_helpb_en : std_logic;
signal s_intpre2_d : std_logic;
signal s_intpre2_en: std_logic;
signal s_intlow_d : std_logic;
signal s_intlow_en : std_logic;
signal s_inthigh_d : std_logic;
signal s_inthigh_en: std_logic;
signal s_ext0isr_d : std_logic;
signal s_ext0isrh_d : std_logic;
signal s_ext1isr_d : std_logic;
signal s_ext1isrh_d : std_logic;
signal s_nextstate : t_state; -- enable signal for state
signal s_bit_data : std_logic;
signal s_intpre: std_logic; -- an interrupt must start
signal s_intpre2: std_logic; -- prepare for interrupt
signal s_inthigh: std_logic; -- high priority int is running
signal s_intlow: std_logic; -- low priority int is running
signal s_intblock: std_logic; -- interrupt delay at RETI, IE, IP
signal s_int0_edge : t_ext_l;
signal s_int1_edge : t_ext_l;
signal s_tf0_edge : t_tmr_l;
signal s_tf1_edge : t_tmr_l;
signal s_ri_edge : t_siu_l;
signal s_ti_edge : t_siu_l;
signal s_smodreg : t_siu_l;
signal s_tl0 : t_tmr_us;
signal s_tl1 : t_tmr_us;
signal s_th0 : t_tmr_us;
signal s_th1 : t_tmr_us;
signal s_sbufi : t_siu_us;
signal s_reload : t_tmr_us;
signal s_wt : t_tmr_us2;
signal s_tf1 : std_logic;
signal s_tf0 : std_logic;
signal s_ie1 : std_logic;
signal s_ie0 : std_logic;
signal s_ri : std_logic;
signal s_ti : std_logic;
signal s_rb8 : std_logic;
signal s_tb8 : std_logic;
signal s_ren : std_logic;
signal s_sm2 : std_logic;
signal s_sm1 : std_logic;
signal s_sm0 : std_logic;
signal s_smod : std_logic;
signal s_int0_h1 : t_ext_l; -- help-bit for edge detection
signal s_int0_h2 : t_ext_l;
signal s_int0_h3 : t_ext_l;
signal s_int1_h1 : t_ext_l;
signal s_int1_h2 : t_ext_l;
signal s_int1_h3 : t_ext_l;
signal s_tf0_h1,s_tf0_h2 : t_tmr_l;
signal s_tf1_h1,s_tf1_h2 : t_tmr_l;
signal s_ri_h1,s_ri_h2 : t_siu_l;
signal s_ti_h1,s_ti_h2 : t_siu_l;
signal s_tsel : muxint;
signal s_ssel : muxint;
signal s_p : std_logic;
signal s_p0 : std_logic_vector(7 downto 0);
signal s_p1 : std_logic_vector(7 downto 0);
signal s_p2 : std_logic_vector(7 downto 0);
signal s_p3 : std_logic_vector(7 downto 0);
signal pc: unsigned(15 downto 0); -- program counter register
signal pc_comb: unsigned(15 downto 0); -- program counter
signal pc_plus1: unsigned(15 downto 0); -- program counter + 1
signal pc_plus2: unsigned(15 downto 0); -- program counter + 2
signal s_data : unsigned(7 downto 0);
signal s_adr : unsigned(7 downto 0);
signal s_preadr : unsigned(7 downto 0);
signal s_bdata : std_logic;
signal s_rr_adr : unsigned (7 downto 0);
signal s_ri_adr : std_logic_vector (7 downto 0);
signal s_ri_data : unsigned (7 downto 0);
-- 8051 standard special-function-register (SFR)
signal p0: unsigned(7 downto 0);
signal sp: unsigned(7 downto 0);
signal dpl: unsigned(7 downto 0);
signal dph: unsigned(7 downto 0);
signal pcon: unsigned(3 downto 0);
signal tcon: t_tmr_lv;
signal tmod: t_tmr_us;
signal p1: unsigned(7 downto 0);
signal scon: t_siu_lv;
signal sbuf: t_siu_us;
signal p2: unsigned(7 downto 0);
signal ie: std_logic_vector(7 downto 0);
signal p3: unsigned(7 downto 0);
signal ip: std_logic_vector(7 downto 0);
signal psw: std_logic_vector(7 downto 0);
signal acc: unsigned(7 downto 0);
signal b: unsigned(7 downto 0);
-- 8051 extended special-function-register
signal tsel: unsigned(7 downto 0); -- select a Timer-Unit
signal ssel: unsigned(7 downto 0); -- select a SIU-Unit
alias CY : std_logic is psw(7);
alias AC : std_logic is psw(6);
alias OV : std_logic is psw(2);
alias EA: std_logic is ie(7);
alias ES: std_logic is ie(4);
alias ET1: std_logic is ie(3);
alias EX1: std_logic is ie(2);
alias ET0: std_logic is ie(1);
alias EX0: std_logic is ie(0);
alias PS0: std_logic is ip(4);
alias PT1: std_logic is ip(3);
alias PX1: std_logic is ip(2);
alias PT0: std_logic is ip(1);
alias PX0: std_logic is ip(0);
begin
-- some simple assignments
pc_o <= std_logic_vector(pc_comb);
pc_plus1 <= pc + conv_unsigned(1,1);
pc_plus2 <= pc + conv_unsigned(2,2);
ram_adr_o <= std_logic_vector(s_adr(6 downto 0));
reg_data_o <= std_logic_vector(s_reg_data);
ram_data_o <= std_logic_vector(s_data);
acc_o <= std_logic_vector(acc);
cy_o(1) <= cy;
ov_o <= ov;
cy_o(0) <= ac;
ie_o <= ie;
ip_o <= ip;
psw_o <= psw;
state_o <= state;
command_o <= s_command;
ri_o <= s_ri;
ti_o <= s_ti;
help_o <= std_logic_vector(s_help);
bit_data_o <= s_bit_data;
intpre_o <= s_intpre;
intpre2_o <= s_intpre2;
inthigh_o <= s_inthigh;
intlow_o <= s_intlow;
tf1_o <= s_tf1;
tf0_o <= s_tf0;
ie1_o <= s_ie1;
ie0_o <= s_ie0;
s_pc_inc_en <= pc_inc_en_i;
s_nextstate <= nextstate_i;
s_adr_mux <= adr_mux_i;
s_adrx_mux <= adrx_mux_i;
s_data_mux <= data_mux_i;
s_bdata_mux <= bdata_mux_i;
s_regs_wr_en <= regs_wr_en_i;
s_help_en <= help_en_i;
s_help16_en <= help16_en_i;
s_helpb_en <= helpb_en_i;
s_inthigh_en <= inthigh_en_i;
s_intlow_en <= intlow_en_i;
s_intpre2_en <= intpre2_en_i;
s_inthigh_d <= inthigh_d_i;
s_intlow_d <= intlow_d_i;
s_intpre2_d <= intpre2_d_i;
s_tsel <= conv_integer(tsel) when tsel < C_IMPL_N_TMR
else conv_integer(0); -- selected timer unit is (not) implemented
s_ssel <= conv_integer(ssel) when ssel < C_IMPL_N_SIU
else conv_integer(0); -- selected siu unit is (not) implemented
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