tb_mc8051_tmrctr_sim.vhd

FPGA的51内核（全）

    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(255,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(255,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(153,8);     -- "10011001"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 640;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;
    
-------------------------------------------------------------------------------
-- Testing MODE 2
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- set the two timer/counters in mode 2 as timers
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(250,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(250,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(34,8);      -- "00100010"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 640;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;

-------------------------------------------------------------------------------
-- set the two timer/counters in mode 2 as counters
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(102,8);     -- "01100110"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 1280;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;

-------------------------------------------------------------------------------
-- set the two timer/counters in mode 2 as counters using interrupt inputs
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(238,8);     -- "11101110"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 1280;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;
    
-------------------------------------------------------------------------------
-- set the two timer/counters in mode 2 as timers using interrupt inputs
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(170,8);          -- "101010101"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 800;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;
    
-------------------------------------------------------------------------------
-- Testing MODE 3
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- set the two timer/counters in mode 3 as timers
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(51,8);           -- "00110011"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 960;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;

-------------------------------------------------------------------------------
-- set the two timer/counters in mode 3 as counters
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(119,8);           -- "01110111"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 960;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;

-------------------------------------------------------------------------------
-- set the two timer/counters in mode 3 as counters using interrupt inputs
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(255,8);          -- "11111111"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 960;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;
    
-------------------------------------------------------------------------------
-- set the two timer/counters in mode 3 as timers using interrupt inputs
-------------------------------------------------------------------------------
    -- Perform reloads of tmr/ctr registers
    s_wt <= conv_std_logic_vector(0,2);         -- TL0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(1,2);         -- TL1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(252,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(2,2);         -- TH0
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt <= conv_std_logic_vector(3,2);         -- TH1
    s_wt_en <= '1';
    s_reload <= conv_std_logic_vector(253,8);   -- reload value
    wait for one_period;
    s_wt_en <= '0';
    
    s_tmod <= conv_std_logic_vector(187,8);          -- "10111011"
    s_tcon_tr0 <= '1';    
    s_tcon_tr1 <= '1';
    wait for one_period * 960;
    s_tcon_tr0 <= '0';    
    s_tcon_tr1 <= '0';
    wait for one_period * 4;

    wait for one_period * 10;
    assert FALSE report "END OF SIMULATION" severity failure;
    
-------------------------------------------------------------------------------
-- END of test after ~1000 * one_period
-------------------------------------------------------------------------------

end process p_run;


-- system clock definition

p_clock:   process
    
   variable  v_loop1 :   integer;
   
   begin
   clk <= '0';
   wait for one_period / 2;
   while true loop
      clk <= not clk;
      wait for one_period / 2;
   end loop;
   
end process p_clock;

p_tx:   process                       -- stimulate external inputs
    
   variable  v_loop1 :   integer;
   
   begin
   s_t0 <= '0';
   s_t1 <= '0';
   wait for one_period / 4;
   while true loop
      s_t0 <= not s_t0;
      s_t1 <= not s_t1;
      
      wait for one_period * 32;
   end loop;
   
end process p_tx;

p_intx:   process                       -- stimulate external inputs
    
   variable  v_loop1 :   integer;
   
   begin
   s_int0 <= '0';
   s_int1 <= '0';
   wait for one_period / 4;
   while true loop
      s_int0 <= not s_int0;
      s_int1 <= not s_int1;      
      wait for one_period * 64;
   end loop;
   
end process p_intx;

p_description: process(s_tmod)

begin

case s_tmod(3 downto 0) is
    when "0000" => tmr_ctr0 <= MODE0_timer;
    when "1000" => tmr_ctr0 <= MODE0_timer_interrupt;
    when "0100" => tmr_ctr0 <= MODE0_counter;
    when "1100" => tmr_ctr0 <= MODE0_counter_interrupt;
    when "0001" => tmr_ctr0 <= MODE1_timer;
    when "1001" => tmr_ctr0 <= MODE1_timer_interrupt;
    when "0101" => tmr_ctr0 <= MODE1_counter;
    when "1101" => tmr_ctr0 <= MODE1_counter_interrupt;
    when "0010" => tmr_ctr0 <= MODE2_timer;
    when "1010" => tmr_ctr0 <= MODE2_timer_interrupt;
    when "0110" => tmr_ctr0 <= MODE2_counter;
    when "1110" => tmr_ctr0 <= MODE2_counter_interrupt;
    when "0011" => tmr_ctr0 <= MODE3_timer;
    when "1011" => tmr_ctr0 <= MODE3_timer_interrupt;
    when "0111" => tmr_ctr0 <= MODE3_counter;
    when "1111" => tmr_ctr0 <= MODE3_counter_interrupt;
    when others => tmr_ctr0 <= SIMULATION_ERROR;
end case;

case s_tmod(7 downto 4) is
    when "0000" => tmr_ctr1 <= MODE0_timer;
    when "1000" => tmr_ctr1 <= MODE0_timer_interrupt;
    when "0100" => tmr_ctr1 <= MODE0_counter;
    when "1100" => tmr_ctr1 <= MODE0_counter_interrupt;
    when "0001" => tmr_ctr1 <= MODE1_timer;
    when "1001" => tmr_ctr1 <= MODE1_timer_interrupt;
    when "0101" => tmr_ctr1 <= MODE1_counter;
    when "1101" => tmr_ctr1 <= MODE1_counter_interrupt;
    when "0010" => tmr_ctr1 <= MODE2_timer;
    when "1010" => tmr_ctr1 <= MODE2_timer_interrupt;
    when "0110" => tmr_ctr1 <= MODE2_counter;
    when "1110" => tmr_ctr1 <= MODE2_counter_interrupt;
    when "0011" => tmr_ctr1 <= MODE3_timer;
    when "1011" => tmr_ctr1 <= MODE3_timer_interrupt;
    when "0111" => tmr_ctr1 <= MODE3_counter;
    when "1111" => tmr_ctr1 <= MODE3_counter_interrupt;
    when others => tmr_ctr1 <= SIMULATION_ERROR;
end case;

end process p_description;

end sim;