receice.rpt

RS232通讯VHDL源代码,MAXPLUS 2环境执行通过

sbuf3    = uart_buf4~NOT;
uart_buf4~NOT = TFFE( _EQ024,  clock_pluse,  VCC,  VCC,  VCC);
  _EQ024 =  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg &  sbuf3 & !sbuf4
         #  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg & !sbuf3 &  sbuf4;

-- Node name is 'sbuf4' = 'uart_buf5' 
-- Equation name is 'sbuf4', location is LC059, type is output.
sbuf4    = uart_buf5~NOT;
uart_buf5~NOT = TFFE( _EQ025,  clock_pluse,  VCC,  VCC,  VCC);
  _EQ025 =  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg &  sbuf4 & !sbuf5
         #  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg & !sbuf4 &  sbuf5;

-- Node name is 'sbuf5' = 'uart_buf6' 
-- Equation name is 'sbuf5', location is LC057, type is output.
sbuf5    = uart_buf6~NOT;
uart_buf6~NOT = TFFE( _EQ026,  clock_pluse,  VCC,  VCC,  VCC);
  _EQ026 =  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg &  sbuf5 & !sbuf6
         #  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg & !sbuf5 &  sbuf6;

-- Node name is 'sbuf6' = 'uart_buf7' 
-- Equation name is 'sbuf6', location is LC056, type is output.
sbuf6    = uart_buf7~NOT;
uart_buf7~NOT = TFFE( _EQ027,  clock_pluse,  VCC,  VCC,  VCC);
  _EQ027 =  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg &  sbuf6 & !sbuf7
         #  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg & !sbuf6 &  sbuf7;

-- Node name is 'sbuf7' = 'uart_buf8' 
-- Equation name is 'sbuf7', location is LC053, type is output.
sbuf7    = uart_buf8~NOT;
uart_buf8~NOT = TFFE( _EQ028,  clock_pluse,  VCC,  VCC,  VCC);
  _EQ028 =  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg &  sbuf7 &  uart_buf9
         #  count_reg0 &  count_reg1 &  count_reg2 & !count_reg3 & 
              rxd_start_reg & !sbuf7 & !uart_buf9;

-- Node name is ':385' = 'uart_buf9' 
-- Equation name is 'uart_buf9', location is LC058, type is buried.
uart_buf9 = TFFE( _EQ029,  clock_pluse,  VCC,  VCC,  VCC);
  _EQ029 =  bit_collect0 &  bit_collect1 &  count_reg0 & !_LC049 & !_LC051 & 
              _LC052 &  rxd_start_reg & !uart_buf9 &  _X001
         #  count_reg0 & !_LC049 & !_LC051 &  _LC052 &  rxd &  rxd_start_reg & 
             !uart_buf9 &  _X001 &  _X014
         # !bit_collect1 &  count_reg0 & !_LC049 & !_LC051 &  _LC052 & 
              rxd_start_reg &  uart_buf9 &  _X001 &  _X015
         # !bit_collect0 &  count_reg0 & !_LC049 & !_LC051 &  _LC052 & !rxd & 
              rxd_start_reg &  uart_buf9 &  _X001;
  _X001  = EXP( count_reg1 &  count_reg2 &  count_reg3);
  _X014  = EXP(!bit_collect0 & !bit_collect1);
  _X015  = EXP( bit_collect0 &  rxd);

-- Node name is '|lpm_add_sub:411|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried 
_LC050   = LCELL(!clock_div1 $ !clock_div0);

-- Node name is '|lpm_add_sub:411|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC054', type is buried 
_LC054   = LCELL( clock_div2 $  _EQ030);
  _EQ030 =  clock_div0 &  clock_div1;

-- Node name is '|lpm_add_sub:411|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC055', type is buried 
_LC055   = LCELL( clock_div3 $  _EQ031);
  _EQ031 =  clock_div0 &  clock_div1 &  clock_div2;

-- Node name is '|lpm_add_sub:411|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC123', type is buried 
_LC123   = LCELL( clock_div4 $  _EQ032);
  _EQ032 =  clock_div0 &  clock_div1 &  clock_div2 &  clock_div3;

-- Node name is '|lpm_add_sub:411|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC119', type is buried 
_LC119   = LCELL( clock_div5 $  _EQ033);
  _EQ033 =  clock_div0 &  clock_div1 &  clock_div2 &  clock_div3 & 
              clock_div4;

-- Node name is '|lpm_add_sub:411|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC115', type is buried 
_LC115   = LCELL( clock_div6 $  _EQ034);
  _EQ034 =  clock_div0 &  clock_div1 &  clock_div2 &  clock_div3 & 
              clock_div4 &  clock_div5;

-- Node name is '|lpm_add_sub:412|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC049', type is buried 
_LC049   = LCELL(!count_reg1 $ !count_reg0);

-- Node name is '|lpm_add_sub:412|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC051', type is buried 
_LC051   = LCELL( count_reg2 $  _EQ035);
  _EQ035 =  count_reg0 &  count_reg1;

-- Node name is '|lpm_add_sub:412|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC052', type is buried 
_LC052   = LCELL( count_reg3 $  _EQ036);
  _EQ036 =  count_reg0 &  count_reg1 &  count_reg2;

-- Node name is '|lpm_add_sub:413|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried 
_LC047   = LCELL(!bit_cnt1 $ !bit_cnt0);

-- Node name is '|lpm_add_sub:413|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC034', type is buried 
_LC034   = LCELL( bit_cnt2 $  _EQ037);
  _EQ037 =  bit_cnt0 &  bit_cnt1;

-- Node name is '|lpm_add_sub:413|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC045', type is buried 
_LC045   = LCELL( bit_cnt3 $  _EQ038);
  _EQ038 =  bit_cnt0 &  bit_cnt1 &  bit_cnt2;

-- Node name is '~321~1' 
-- Equation name is '~321~1', location is LC038, type is buried.
-- synthesized logic cell 
_LC038   = LCELL( _EQ039 $  GND);
  _EQ039 =  count_reg0 & !count_reg1 & !_LC034 &  _LC045 &  _LC047 & !_LC049 & 
             !_LC051 &  _LC052 &  rxd_start_reg
         #  count_reg0 & !count_reg2 & !_LC034 &  _LC045 &  _LC047 & !_LC049 & 
             !_LC051 &  _LC052 &  rxd_start_reg
         #  count_reg0 & !count_reg3 & !_LC034 &  _LC045 &  _LC047 & !_LC049 & 
             !_LC051 &  _LC052 &  rxd_start_reg
         #  count_reg0 & !count_reg1 &  _LC034 &  _LC045 & !_LC049 & !_LC051 & 
              _LC052 &  rxd_start_reg
         #  count_reg0 & !count_reg2 &  _LC034 &  _LC045 & !_LC049 & !_LC051 & 
              _LC052 &  rxd_start_reg;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                      c:\maxplus2\files\receive\receice.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:02
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,698K