send.rpt

RS232通讯VHDL源代码,MAXPLUS 2环境执行通过

-- Equation name is '~449~1', location is LC126, type is buried.
-- synthesized logic cell 
_LC126   = LCELL( _EQ051 $  GND);
  _EQ051 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  _LC005
         # !bitcnt_reg3 &  _LC005;

-- Node name is '~450~1' 
-- Equation name is '~450~1', location is LC112, type is buried.
-- synthesized logic cell 
_LC112   = LCELL( _EQ052 $ !key_start);
  _EQ052 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  bitcnt_reg3 & 
             !key_start &  _X002
         #  bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2 & !bitcnt_reg3 & 
             !key_start
         # !bitcnt_reg3 &  key_start &  _X002;
  _X002  = EXP( bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2);

-- Node name is '~465~1' 
-- Equation name is '~465~1', location is LC111, type is buried.
-- synthesized logic cell 
_LC111   = LCELL( _EQ053 $  VCC);
  _EQ053 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2
         #  bitcnt_reg3 &  key_start
         # !bitcnt_reg0 & !bitcnt_reg3;

-- Node name is '~466~1' 
-- Equation name is '~466~1', location is LC110, type is buried.
-- synthesized logic cell 
_LC110   = LCELL( _EQ054 $  GND);
  _EQ054 = !bitcnt_reg0 &  bitcnt_reg1 & !bitcnt_reg3
         #  bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg3;

-- Node name is '~467~1' 
-- Equation name is '~467~1', location is LC128, type is buried.
-- synthesized logic cell 
_LC128   = LCELL( _EQ055 $  GND);
  _EQ055 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  _LC005
         # !bitcnt_reg3 &  _LC005;

-- Node name is '~468~1' 
-- Equation name is '~468~1', location is LC109, type is buried.
-- synthesized logic cell 
_LC109   = LCELL( _EQ056 $ !key_start);
  _EQ056 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  bitcnt_reg3 & 
             !key_start &  _X002
         #  bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2 & !bitcnt_reg3 & 
             !key_start
         # !bitcnt_reg3 &  key_start &  _X002;
  _X002  = EXP( bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2);

-- Node name is '~483~1' 
-- Equation name is '~483~1', location is LC003, type is buried.
-- synthesized logic cell 
_LC003   = LCELL( _EQ057 $  GND);
  _EQ057 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2
         #  bitcnt_reg3 &  key_start
         # !bitcnt_reg0 & !bitcnt_reg3;

-- Node name is '~484~1' 
-- Equation name is '~484~1', location is LC108, type is buried.
-- synthesized logic cell 
_LC108   = LCELL( _EQ058 $  GND);
  _EQ058 = !bitcnt_reg0 &  bitcnt_reg1 & !bitcnt_reg3
         #  bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg3;

-- Node name is '~485~1' 
-- Equation name is '~485~1', location is LC127, type is buried.
-- synthesized logic cell 
_LC127   = LCELL( _EQ059 $  GND);
  _EQ059 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  _LC005
         # !bitcnt_reg3 &  _LC005;

-- Node name is '~486~1' 
-- Equation name is '~486~1', location is LC009, type is buried.
-- synthesized logic cell 
_LC009   = LCELL( _EQ060 $ !key_start);
  _EQ060 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  bitcnt_reg3 & 
             !key_start &  _X002
         #  bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2 & !bitcnt_reg3 & 
             !key_start
         # !bitcnt_reg3 &  key_start &  _X002;
  _X002  = EXP( bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2);

-- Node name is '~500~1' 
-- Equation name is '~500~1', location is LC125, type is buried.
-- synthesized logic cell 
_LC125   = LCELL( _EQ061 $  GND);
  _EQ061 =  bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2 & !bitcnt_reg3 & 
             !_LC005;

-- Node name is '~518~1' 
-- Equation name is '~518~1', location is LC113, type is buried.
-- synthesized logic cell 
_LC113   = LCELL( _EQ062 $  GND);
  _EQ062 = !bitcnt_reg0 & !bitcnt_reg1 & !bitcnt_reg2 &  bitcnt_reg3 & 
             !_LC005 &  _X002
         #  bitcnt_reg2 &  bitcnt_reg3 &  key_start
         #  bitcnt_reg1 &  bitcnt_reg3 &  key_start
         #  bitcnt_reg0 &  bitcnt_reg3 &  key_start;
  _X002  = EXP( bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2);

-- Node name is '~534~1' 
-- Equation name is '~534~1', location is LC115, type is buried.
-- synthesized logic cell 
_LC115   = LCELL( _EQ063 $  _EQ064);
  _EQ063 =  bitcnt_reg0 &  bitcnt_reg1 & !bitcnt_reg3 & !_LC005 & !_LC113 & 
              _X002 &  _X011 &  _X012 &  _X013 &  _X014 &  _X015 &  _X016 & 
              _X017 &  _X018
         #  _LC003 &  _LC009 &  _LC108 & !_LC113 & !_LC125 &  _LC127 &  _X011 & 
              _X013 &  _X014 &  _X015 &  _X016 &  _X017 &  _X018
         #  _LC109 &  _LC110 &  _LC111 & !_LC113 & !_LC125 &  _LC128 &  _X011 & 
              _X013 &  _X014 &  _X015 &  _X016 &  _X017 &  _X018
         #  _LC103 &  _LC104 &  _LC112 & !_LC113 & !_LC125 &  _LC126 &  _X011 & 
              _X013 &  _X014 &  _X015 &  _X016 &  _X017 &  _X018;
  _X002  = EXP( bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2);
  _X011  = EXP( bitcnt_reg0 &  bitcnt_reg3 & !key_start);
  _X012  = EXP( bitcnt_reg0 &  bitcnt_reg1 &  bitcnt_reg2 & !bitcnt_reg3 & 
             !_LC005);
  _X013  = EXP( _LC099 &  _LC100 &  _LC101 &  _LC118);
  _X014  = EXP( _LC105 &  _LC114 &  _LC119 &  _LC120);
  _X015  = EXP( _LC106 &  _LC116 &  _LC117 &  _LC124);
  _X016  = EXP( _LC107 &  _LC121 &  _LC122 &  _LC123);
  _X017  = EXP( bitcnt_reg2 &  bitcnt_reg3 & !key_start);
  _X018  = EXP( bitcnt_reg1 &  bitcnt_reg3 & !key_start);
  _EQ064 = !_LC113 & !_LC125 &  _X011 &  _X013 &  _X014 &  _X015 &  _X016 & 
              _X017 &  _X018;
  _X011  = EXP( bitcnt_reg0 &  bitcnt_reg3 & !key_start);
  _X013  = EXP( _LC099 &  _LC100 &  _LC101 &  _LC118);
  _X014  = EXP( _LC105 &  _LC114 &  _LC119 &  _LC120);
  _X015  = EXP( _LC106 &  _LC116 &  _LC117 &  _LC124);
  _X016  = EXP( _LC107 &  _LC121 &  _LC122 &  _LC123);
  _X017  = EXP( bitcnt_reg2 &  bitcnt_reg3 & !key_start);
  _X018  = EXP( bitcnt_reg1 &  bitcnt_reg3 & !key_start);

-- Node name is '~535~1' 
-- Equation name is '~535~1', location is LC102, type is buried.
-- synthesized logic cell 
_LC102   = LCELL( _EQ065 $  VCC);
  _EQ065 = !_LC113 & !_LC115 &  _X019 &  _X020 &  _X021 &  _X022 &  _X023;
  _X019  = EXP( _LC012 &  _LC099 &  _LC100 &  _LC101 &  _LC118);
  _X020  = EXP( _LC003 &  _LC009 &  _LC108 &  _LC127);
  _X021  = EXP( _LC010 &  _LC105 &  _LC114 &  _LC119 &  _LC120);
  _X022  = EXP( _LC013 &  _LC106 &  _LC116 &  _LC117 &  _LC124);
  _X023  = EXP( _LC011 &  _LC107 &  _LC121 &  _LC122 &  _LC123);

-- Node name is '~547~1' 
-- Equation name is '~547~1', location is LC002, type is buried.
-- synthesized logic cell 
_LC002   = LCELL( _EQ066 $  VCC);
  _EQ066 =  _X003 &  _X004 &  _X005 &  _X006 &  _X007 &  _X008 &  _X009 & 
              _X010;
  _X003  = EXP( key_send0 &  key_send1 & !key_send2 &  key_send3 &  key_send4 & 
              key_send5 &  key_send6 &  key_send7);
  _X004  = EXP( key_send0 & !key_send1 &  key_send2 &  key_send3 &  key_send4 & 
              key_send5 &  key_send6 &  key_send7);
  _X005  = EXP( key_send0 &  key_send1 &  key_send2 & !key_send3 &  key_send4 & 
              key_send5 &  key_send6 &  key_send7);
  _X006  = EXP( key_send0 &  key_send1 &  key_send2 &  key_send3 &  key_send4 & 
             !key_send5 &  key_send6 &  key_send7);
  _X007  = EXP( key_send0 &  key_send1 &  key_send2 &  key_send3 &  key_send4 & 
              key_send5 & !key_send6 &  key_send7);
  _X008  = EXP( key_send0 &  key_send1 &  key_send2 &  key_send3 & !key_send4 & 
              key_send5 &  key_send6 &  key_send7);
  _X009  = EXP( key_send0 &  key_send1 &  key_send2 &  key_send3 &  key_send4 & 
              key_send5 &  key_send6 & !key_send7);
  _X010  = EXP(!key_send0 &  key_send1 &  key_send2 &  key_send3 &  key_send4 & 
              key_send5 &  key_send6 &  key_send7);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X002 occurs in LABs A, G, H




Project Information                            c:\maxplus2\files\send\send.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:03
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   --------------------------