📄 send.rpt
字号:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\files\send\send.rpt
send
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(45) 67 E SOFT t 0 0 0 0 2 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node1
- 87 F SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node2
- 92 F SOFT t 0 0 0 0 4 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node3
(62) 96 F SOFT t 0 0 0 0 5 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node4
(56) 86 F SOFT t 0 0 0 0 6 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node5
(55) 85 F SOFT t 0 0 0 0 7 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node6
- 84 F SOFT t 0 0 0 0 8 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node7
(54) 83 F SOFT t 0 0 0 0 9 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder1|result_node0
(60) 93 F SOFT t 0 0 0 0 10 0 1 |lpm_add_sub:550|addcore:adder|addcore:adder1|result_node1
- 15 A SOFT t 0 0 0 0 3 0 1 |lpm_add_sub:551|addcore:adder|addcore:adder0|gcp2
(11) 5 A SOFT t 0 0 0 0 3 0 11 |lpm_add_sub:551|addcore:adder|addcore:adder0|result_node2
- 81 F DFFE + t 0 0 0 0 11 0 12 count10 (:89)
- 82 F DFFE + t 0 0 0 0 5 0 13 count9 (:90)
- 89 F DFFE + t 0 0 0 0 5 0 14 count8 (:91)
- 90 F DFFE + t 0 0 0 0 5 0 15 count7 (:92)
- 95 F DFFE + t 0 0 0 0 5 0 5 count6 (:93)
(9) 8 A DFFE + t 0 0 0 0 5 0 6 count5 (:94)
- 7 A DFFE + t 0 0 0 0 5 0 7 count4 (:95)
(10) 6 A DFFE + t 0 0 0 0 5 0 8 count3 (:96)
- 4 A DFFE + t 0 0 0 0 5 0 9 count2 (:97)
(61) 94 F DFFE + t 0 0 0 0 5 0 10 count1 (:98)
(58) 91 F DFFE + t 0 0 0 0 5 0 11 count0 (:99)
(57) 88 F DFFE + t 0 0 0 0 4 1 4 bit_start (:103)
(4) 16 A DFFE t 2 1 0 1 6 0 35 bitcnt_reg3 (:180)
- 1 A DFFE t 0 0 0 0 6 0 29 bitcnt_reg2 (:181)
- 98 G DFFE t 0 0 0 0 4 0 37 bitcnt_reg1 (:182)
(63) 97 G DFFE t 0 0 0 1 5 0 37 bitcnt_reg0 (:183)
- 121 H SOFT s t 0 0 0 1 4 0 2 ~215~1
(69) 107 G SOFT s t 0 0 0 0 3 0 2 ~216~1
(77) 123 H SOFT s t 0 0 0 0 5 0 2 ~217~1
- 122 H SOFT s t 1 1 0 1 4 0 2 ~218~1
- 12 A SOFT s t 4 3 1 8 0 0 1 ~375~1
- 10 A SOFT s t 0 0 0 8 0 0 1 ~376~1
(6) 13 A SOFT s t 0 0 0 8 0 0 1 ~377~1
(8) 11 A SOFT s t 0 0 0 8 0 0 1 ~378~1
(74) 117 H SOFT s t 0 0 0 1 4 0 2 ~393~1
- 106 G SOFT s t 0 0 0 0 3 0 2 ~394~1
- 116 H SOFT s t 0 0 0 0 5 0 2 ~395~1
- 124 H SOFT s t 1 1 0 1 4 0 2 ~396~1
- 114 H SOFT s t 0 0 0 1 4 0 2 ~411~1
(68) 105 G SOFT s t 0 0 0 0 3 0 2 ~412~1
- 119 H SOFT s t 0 0 0 0 5 0 2 ~413~1
(76) 120 H SOFT s t 1 1 0 1 4 0 2 ~414~1
(65) 101 G SOFT s t 0 0 0 1 4 0 2 ~429~1
- 100 G SOFT s t 0 0 0 0 3 0 2 ~430~1
(75) 118 H SOFT s t 0 0 0 0 5 0 2 ~431~1
(64) 99 G SOFT s t 1 1 0 1 4 0 2 ~432~1
- 103 G SOFT s t 0 0 0 1 4 0 1 ~447~1
(67) 104 G SOFT s t 0 0 0 0 3 0 1 ~448~1
(80) 126 H SOFT s t 0 0 0 0 5 0 1 ~449~1
(71) 112 G SOFT s t 1 1 0 1 4 0 1 ~450~1
- 111 G SOFT s t 0 0 0 1 4 0 1 ~465~1
- 110 G SOFT s t 0 0 0 0 3 0 1 ~466~1
(81) 128 H SOFT s t 0 0 0 0 5 0 1 ~467~1
(70) 109 G SOFT s t 1 1 0 1 4 0 1 ~468~1
(12) 3 A SOFT s t 0 0 0 1 4 0 2 ~483~1
- 108 G SOFT s t 0 0 0 0 3 0 2 ~484~1
- 127 H SOFT s t 0 0 0 0 5 0 2 ~485~1
- 9 A SOFT s t 1 1 0 1 4 0 2 ~486~1
(79) 125 H SOFT s t 0 0 0 0 5 0 1 ~500~1
- 113 H SOFT s t 1 1 0 1 5 0 2 ~518~1
(73) 115 H SOFT s t 10 1 1 1 35 0 1 ~534~1
- 102 G SOFT s t 5 0 0 0 26 1 0 ~535~1
- 2 A SOFT s t 8 8 0 8 0 1 0 ~547~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\maxplus2\files\send\send.rpt
send
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC15 |lpm_add_sub:551|addcore:adder|addcore:adder0|gcp2
| +----------------------------- LC5 |lpm_add_sub:551|addcore:adder|addcore:adder0|result_node2
| | +--------------------------- LC14 txd
| | | +------------------------- LC8 count5
| | | | +----------------------- LC7 count4
| | | | | +--------------------- LC6 count3
| | | | | | +------------------- LC4 count2
| | | | | | | +----------------- LC16 bitcnt_reg3
| | | | | | | | +--------------- LC1 bitcnt_reg2
| | | | | | | | | +------------- LC12 ~375~1
| | | | | | | | | | +----------- LC10 ~376~1
| | | | | | | | | | | +--------- LC13 ~377~1
| | | | | | | | | | | | +------- LC11 ~378~1
| | | | | | | | | | | | | +----- LC3 ~483~1
| | | | | | | | | | | | | | +--- LC9 ~486~1
| | | | | | | | | | | | | | | +- LC2 ~547~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC15 -> - - - - - - - * - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:551|addcore:adder|addcore:adder0|gcp2
LC5 -> - - - - - - - - * - - - - - - - | * - - - - - - * | <-- |lpm_add_sub:551|addcore:adder|addcore:adder0|result_node2
LC14 -> - - * - - - - - - - - - - - - - | * - - - - - - - | <-- txd
LC16 -> - - - - - - - * * - - - - * * - | * - - - - - * * | <-- bitcnt_reg3
LC1 -> * * - - - - - * * - - - - * * - | * - - - - - * * | <-- bitcnt_reg2
LC2 -> - - * - - - - - - - - - - - - - | * - - - - - - - | <-- ~547~1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
56 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send0
57 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send1
58 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send2
60 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send3
61 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send4
63 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send5
64 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send6
65 -> - - * - - - - - - * * * * - - * | * - - - - - - - | <-- key_send7
2 -> - - - - - - - * - - - - - * * - | * - - - - - * * | <-- key_start
LC87 -> - - - - - - * - - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node2
LC92 -> - - - - - * - - - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node3
LC96 -> - - - - * - - - - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node4
LC86 -> - - - * - - - - - - - - - - - - | * - - - - - - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node5
LC81 -> - - - * * * * - - - - - - - - - | * - - - - * - - | <-- count10
LC82 -> - - - * * * * - - - - - - - - - | * - - - - * - - | <-- count9
LC89 -> - - - * * * * - - - - - - - - - | * - - - - * - - | <-- count8
LC90 -> - - - * * * * - - - - - - - - - | * - - - - * - - | <-- count7
LC88 -> - - * - - - - * * - - - - - - - | * - - - - - * - | <-- bit_start
LC98 -> * * - - - - - * * - - - - * * - | * - - - - - * * | <-- bitcnt_reg1
LC97 -> * * - - - - - * * - - - - * * - | * - - - - - * * | <-- bitcnt_reg0
LC102-> - - * - - - - - - - - - - - - - | * - - - - - - - | <-- ~535~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\files\send\send.rpt
send
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+- LC67 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node1
|
| Other LABs fed by signals
| that feed LAB 'E'
LC | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
83 -> - | - - - - - - - - | <-- clock
2 -> - | * - - - - - * * | <-- key_start
LC94 -> * | - - - - * * - - | <-- count1
LC91 -> * | - - - - * * - - | <-- count0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\files\send\send.rpt
send
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+------------------------------- LC87 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node2
| +----------------------------- LC92 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node3
| | +--------------------------- LC96 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node4
| | | +------------------------- LC86 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node5
| | | | +----------------------- LC85 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node6
| | | | | +--------------------- LC84 |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node7
| | | | | | +------------------- LC83 |lpm_add_sub:550|addcore:adder|addcore:adder1|result_node0
| | | | | | | +----------------- LC93 |lpm_add_sub:550|addcore:adder|addcore:adder1|result_node1
| | | | | | | | +--------------- LC81 count10
| | | | | | | | | +------------- LC82 count9
| | | | | | | | | | +----------- LC89 count8
| | | | | | | | | | | +--------- LC90 count7
| | | | | | | | | | | | +------- LC95 count6
| | | | | | | | | | | | | +----- LC94 count1
| | | | | | | | | | | | | | +--- LC91 count0
| | | | | | | | | | | | | | | +- LC88 bit_start
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC85 -> - - - - - - - - - - - - * - - - | - - - - - * - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node6
LC84 -> - - - - - - - - - - - * - - - - | - - - - - * - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node7
LC83 -> - - - - - - - - - - * - - - - - | - - - - - * - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder1|result_node0
LC93 -> - - - - - - - - - * - - - - - - | - - - - - * - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder1|result_node1
LC81 -> - - - - - - - - * * * * * * * * | * - - - - * - - | <-- count10
LC82 -> - - - - - - - * * * * * * * * * | * - - - - * - - | <-- count9
LC89 -> - - - - - - * * * * * * * * * * | * - - - - * - - | <-- count8
LC90 -> - - - - - * * * * * * * * * * * | * - - - - * - - | <-- count7
LC95 -> - - - - * * * * * - - - - - - - | - - - - - * - - | <-- count6
LC94 -> * * * * * * * * * - - - - - - - | - - - - * * - - | <-- count1
LC91 -> * * * * * * * * * - - - - - * - | - - - - * * - - | <-- count0
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clock
2 -> - - - - - - - - - - - - - - - - | * - - - - - * * | <-- key_start
LC67 -> - - - - - - - - - - - - - * - - | - - - - - * - - | <-- |lpm_add_sub:550|addcore:adder|addcore:adder0|result_node1
LC8 -> - - - * * * * * * - - - - - - - | - - - - - * - - | <-- count5
LC7 -> - - * * * * * * * - - - - - - - | - - - - - * - - | <-- count4
LC6 -> - * * * * * * * * - - - - - - - | - - - - - * - - | <-- count3
LC4 -> * * * * * * * * * - - - - - - - | - - - - - * - - | <-- count2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\maxplus2\files\send\send.rpt
send
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------------------------- LC98 bitcnt_reg1
| +----------------------------- LC97 bitcnt_reg0
| | +--------------------------- LC107 ~216~1
| | | +------------------------- LC106 ~394~1
| | | | +----------------------- LC105 ~412~1
| | | | | +--------------------- LC101 ~429~1
| | | | | | +------------------- LC100 ~430~1
| | | | | | | +----------------- LC99 ~432~1
| | | | | | | | +--------------- LC103 ~447~1
| | | | | | | | | +------------- LC104 ~448~1
| | | | | | | | | | +----------- LC112 ~450~1
| | | | | | | | | | | +--------- LC111 ~465~1
| | | | | | | | | | | | +------- LC110 ~466~1
| | | | | | | | | | | | | +----- LC109 ~468~1
| | | | | | | | | | | | | | +--- LC108 ~484~1
| | | | | | | | | | | | | | | +- LC102 ~535~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'G'
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