udualfifo.srp

来自「USBRTL电路的VHDL和Verilog代码」· SRP 代码 · 共 20 行

SCUBA, Version 9.15
ORCA Foundry, Version 9.15
Copyright (c) 1996-1997 Lucent Technologies Inc. All rights reserved.

    Circuit name     : Udualfifo
    Module type      : sdpram
    Address width    : 5
    Ports            : Inputs  : waddr[4:0], datain[7:0], clk, wren, raddr[4:0]
                       Outputs : dataout[7:0]
    I/O buffer       : not inserted
    Clock edge       : rising edge
    Memory mode      : fast
    EDIF output      : suppressed
    Verilog output   : Udualfifo.v
    Verilog template : Udualfifo_tmpl.v
    Verilog purpose  : for synthesis
    Bus notation     : big endian
    Report output    : Udualfifo.srp
    Issued command   : /cad1/orca/bin/sol/scuba -n Udualfifo -e -lang verilog -synth -bb -scubash -bus_exp 4 -type sdpram -addr_width 5 -data_width 8 -fastmode