utop.v

USBRTL电路的VHDL和Verilog代码

/*    
# --------------------------------------------------------------------------
#     
#    Module      : Utop.v 
#     
#    Reviewer(s) :
#    
#    Revision     : $Revision: 1.6 $
#    
#---------------------------------------------------------------------------
#   Purpose : Synthesis top module
#-------------------------------------------------------------------------
*/   


// THIS BLOCK INCLUDES 8051IF 

module Utop
	(
	// inputs from bus
                xin,            // core         - 1
                xout,           // core         - 1
//                clock_in,	
                dp,		// plus in      - 1
                dm,		// minus in     - 1
                // rha spimode,        // spimode      - 1
                //rha enmmc,		// mmc or sm    - 1 
                vidpin,         // core         - 4
                pwronresetb,    // core         - 1
                // inputs from smart media
                card_ready,     // sm           - 1
                io,             // sm           - 8
				// in /out for mmc
                data_cf_in,     // mmc          - 1
                cs_fc_out,      // mmc          - 1
                clock_fc_out,   // mmc          - 1 
                data_fc_out,    // mmc          - 1

                // outputs to smart media
                ale,            // sm           - 1
                ceb,            // sm           - 1
                cle,            // sm           - 1
                reb,            // sm           - 1
                web,            // sm           - 1
                wpb,            // sm           - 1

                avss0,          // top          - 1
                avss1,          // top          - 1
                avdd0,          // top          - 1
                avdd1,          // top          - 1
                dvss0,           // top          - 1
                dvdd0            // top          - 1
                                // total    = 36
	);
  
  input       xin;
  input       xout;

  input       avss0;
  input       avss1;
  input       avdd0;
  input       avdd1;
  input       dvss0;
  input       dvdd0;

  input       dp;
  input       dm;
  //rha input	      enmmc;
  //rha input       spimode;
  input       pwronresetb;
  input [3:0] vidpin;
  input       card_ready;

  inout [7:0] io;
  inout	       data_cf_in;
  inout       data_fc_out;

  output      clock_fc_out;

  output      cs_fc_out;
  output             ale;
  output             ceb;
  output             cle;
  output             reb;
  output             web;
  output             wpb;

wire                 pwronresetb_in;
//rha wire                 enmmc_in;
//rha wire                 spimode_in;
wire                 card_ready_in;
wire    [3:0]        vidpin_in;
wire                 cs_fc_out;
wire                 ale;
wire                 ceb;
wire                 cle;
wire                 reb;
wire                 web;
wire                 wpb;
wire                 clock_fc_out;
wire	             clock_in;

 Utop_mmc_sm  u0_top_mmc_sm (
                // inputs from bus
                .pwronresetb(pwronresetb_in),
                .clock48(clock48),
                .rcvin(rcvin),
                .vpin(vpin),
                .vmin(vmin),
                //rha .enmmc(enmmc_in),
                //rha .spimode(spimode_in),
                .data_cf_in(data_cf_in),
                .card_ready(card_ready_in),
                .vidpin(vidpin_in),
                .io(io),
                .vmo(vmo),
                .vpo(vpo),            // plus out
                .usboen(usboen), // oe for usb bits
                //.usbclock(usbclock),
                .suspend(suspend),
                .cs_fc_out(cs_fc_out),
                .clock_fc_out(clock_fc_out),
                .data_fc_out(data_fc_out),
                .ale(ale),
                .ceb(ceb),
                .cle(cle),
                .reb(reb),
                .web(web),
                .wpb(wpb)
                );

pc3d01      u0_pc3d01 (              // just only input only pad
                       .pad(pwronresetb),
                       .cin(pwronresetb_in)
                      );
/* rha 
pc3d01      u1_pc3d01 (              // just only input only pad
                       .pad(enmmc),
                       .cin(enmmc_in)
                      );  

pc3d01      u2_pc3d01 (              // just only input only pad
                       .pad(spimode),
                       .cin(spimode_in)
                      ); */

pc3d01      u3_pc3d01 (              // just only input only pad
                       .pad(card_ready),
                       .cin(card_ready_in)
                      );

pc3d01      u4_pc3d01 (              // just only input only pad
                       .pad(vidpin[0]),
                       .cin(vidpin_in[0])
                      );

pc3d01      u5_pc3d01 (              // just only input only pad
                       .pad(vidpin[1]),
                       .cin(vidpin_in[1])
                      );

pc3d01      u6_pc3d01 (              // just only input only pad
                       .pad(vidpin[2]),
                       .cin(vidpin_in[2])
                      );

pc3d01      u7_pc3d01 (              // just only input only pad
                       .pad(vidpin[3]),
                       .cin(vidpin_in[3])
                      );
/*
pc3o03      u0_pc3o03 (               // 5 kind of output only pad
                       .i(cs_fc_out_out),
                       .pad(cs_fc_out)
                      );

pc3o03      u1_pc3o03 (               // 5 kind of output only pad
                       .i(ale_out),
                       .pad(ale)
                      );

pc3o03      u2_pc3o03 (               // 5 kind of output only pad
                       .i(ceb_out),
                       .pad(ceb)
                      );

pc3o03      u3_pc3o03 (               // 5 kind of output only pad
                       .i(cle_out),
                       .pad(cle)
                      );

pc3o03      u4_pc3o03 (               // 5 kind of output only pad
                       .i(reb_out),
                       .pad(reb)
                      );

pc3o03      u5_pc3o03 (               // 5 kind of output only pad
                       .i(web_out),
                       .pad(web)
                      );

pc3o03      u6_pc3o03 (               // 5 kind of output only pad
                       .i(wpb_out),
                       .pad(wpb)
                      );

pc3o03      u7_pc3o03 (               // 5 kind of output only pad
                       .i(clock_fc_out_out),
                       .pad(clock_fc_out)
                      ); */

pv0i        u0_pv0i ( .vss(avss0));
pv0i        u1_pv0i ( .vss(avss1));
pvdi        u0_pvdi ( .vdd(avdd0));
pvdi        u1_pvdi ( .vdd(avdd1));
pv0f        u0_pv0f ( .vss(dvss0));
pvdf        u0_pvdf ( .vdd(dvdd0));

pc3x12 u0_pc3x12    ( .z(clock48),    // 3 kind of crystal clock paad
                      .xout(xout), 
                      .xin(xin), 
                      .en(suspend));

usbpad_353b u1_usbpad_353b(
                .IP(DmnsP),
                .IN(DmnsN),
                .PAD(dm)
                );      
    
usbpad_353b u0_usbpad_353b(
                .IP(DplsP),
                .IN(DplsN),
                .PAD(dp)
                );      

utr333d u0_utr333d (
                .OEB (usboen),
                .RCV (rcvin),
                .VP (vpin),
                .VM (vmin),
                .SUSPEND (suspend),
                .VMO (vmo),
                .VPO (vpo),
                .Dpls (dp),
                .Dmns (dm),
                .DmnsP ( DmnsP) ,
                .DmnsN ( DmnsN) ,
                .DplsP ( DplsP) ,
                .DplsN ( DplsN) ,
                .SPEED (1'b1)
                );      

/*
power_on_reset  u0_power_on_reset (
                .reset(pwronreset)
                );

lg3pl11    u0_pll (
                .n(4'b0000),
                .fref(clock_in),
                .m(5'd14),
                .duty(2'b00),
                .reset(suspend),
                .pllenb(suspend),
                .fout(clock48)
                );

*/
endmodule