tri_signal.v

USBRTL电路的VHDL和Verilog代码

/********************************************************
 *    1. File name : tri_bus.v 
 *    3. Key Feature & module : This module( tri_bus ) is
 *           for tri-state  bus between  usb and smart card.
 *
 *     5. modification history
 ********************************************************/

module tri_signal (
                out_enableb, 
                io,
                data_out
              );

  input              out_enableb;
  input              data_out;

  inout              io;

  assign io = ( !out_enableb)? data_out  : 1'bz;

endmodule