usiecrc.v

USBRTL电路的VHDL和Verilog代码

module Usiecrc
	(
	// inputs
		usbclock,
		usbreset,
		rcvdatavalid,
		rcvdatabit,
		rcvcrc5data,
		rcvcrc5check,
		rcvcrc16data,
		rcvcrc16check,
		xmitdatavalid,
		xmitdatabit,
		xmitcrc16data,
		xmitcrc16send,
		xmitactive,		// generate vs. check

	// outputs
		xmitcrcout,
		crcerrordetected,
		crccheckok
	);

`include "Usiecrcdef.v"
`include "Uusbdef.v"

input	usbclock;
input	usbreset;

input	rcvdatavalid;
input	rcvdatabit;
input	rcvcrc5data;
input	rcvcrc5check;
input	rcvcrc16data;
input	rcvcrc16check;

input	xmitdatavalid;
input	xmitdatabit;
input	xmitcrc16data;
input	xmitcrc16send;

input	xmitactive;

output	xmitcrcout;
output		crcerrordetected;
output		crccheckok;

reg		crcerrordetected;
reg		crccheckok;
reg	[15:0]	crcbits;
reg	[15:0]	newcrcbits;		// not really a flop

wire	checkcrc = ~xmitactive;	// get back to original signal polarity


// generate some combined bits for use in unified crc gen/check
wire	crcdatabit = checkcrc ? rcvdatabit : xmitdatabit;
wire	bitdatavalid = checkcrc ? rcvdatavalid : xmitdatavalid;
wire	crc5 = rcvcrc5data;
wire	crc16 = checkcrc ? rcvcrc16data : (xmitcrc16data || xmitcrc16send);
wire	crcdatavalid = (crc5 || crc16) && bitdatavalid;
wire	resetcrc = checkcrc ? (rcvcrc5check || rcvcrc16check) : 
				~(xmitcrc16send || xmitcrc16data);
wire	crc5error = rcvcrc5check && (crcbits[4:0] != CRC5REMAINDER);
wire	crc16error = rcvcrc16check && (crcbits[15:0] != CRC16REMAINDER);
wire	xmitcrcout = ~crcbits[15];	// always take top bit inverted

// always block for grabbing various bits based on the next, current, or previous state
always @(posedge usbclock)
begin
	if (usbreset || resetcrc)
		crcbits <= 16'hffff;
	else if (crcdatavalid)
		crcbits <= newcrcbits;
	else
		crcbits <= crcbits;

	if (usbreset)
		crcerrordetected <= 1'b0;
	else
		crcerrordetected <= (crc5error || crc16error);
	
	if ((rcvcrc5check && ~crc5error) || (rcvcrc16check && ~crc16error))
		crccheckok <= 1'b1;
	else
		crccheckok <= 1'b0;
end
 
always @(crcbits or crc5 or crcdatabit or xmitcrc16send)
begin
	if (crc5)
		newcrcbits[0] = crcdatabit ^ crcbits[4];
	else
		newcrcbits[0] = crcdatabit ^ crcbits[15];

	newcrcbits[1] = crcbits[0];

	if (crc5)
		newcrcbits[2] = crcdatabit ^ crcbits[4] ^ crcbits[1];
	else if (xmitcrc16send)
		newcrcbits[2] = crcbits[1];
	else
		newcrcbits[2] = crcdatabit ^ crcbits[15] ^ crcbits[1];

	newcrcbits[14:3] = crcbits[13:2];
	if (xmitcrc16send)
		newcrcbits[15] = crcbits[14];
	else
		newcrcbits[15] = crcdatabit ^ crcbits[15] ^ crcbits[14];
end

endmodule