udual_mmc_sm.v_sm

USBRTL电路的VHDL和Verilog代码

/*    
# --------------------------------------------------------------------------
# Confidential
# Copyright (c) 1999 Hyundai electronics Ltd
# All rights reserved
#     
#    Module      : Udual_mmc_sm.v 
#     
#    Originator  : USB
#    
#    Project     : USB MP3 DMA
#    
#    Reviewer(s) :
#    
#    RCS Information
#    
#    RCS Filename : $RCSfile: Udual_mmc_sm.v,v $
#    
#    Updated by   : $Author: jakehan $
#    
#    Checked in   : $Date: 1999/12/16 07:27:31 $
#    
#    Revision     : $Revision: 1.24 $
#    
#    State        : $State: Exp $ (Exp/Stable/Reviewed/Released etc.)
#    
#---------------------------------------------------------------------------
#   Purpose : 
#-------------------------------------------------------------------------
*/   

// THIS BLOCK INCLUDES 8051IF 

module Udual_mmc_sm
	(
	// inputs from bus
		pwronresetb,
		clock48,	// 48 MHz clock
		rcvin,		// differential in
		vpin,		// plus in
		vmin,		// minus in
                // inputs from smart media
                card_ready,

		vmo,		// minus out
		vpo,		// plus out
		usboen,	// oe for usb bits
		suspend,
		//usbclock,
          gpiopin0,
		  gpiopin1,
		  gpiopin2,
		  gpiopin3,
		  gpiopin4,
		  gpiopin5,
		  gpiopin6,
		  gpiopin7,
				// in /out for mmc
                data_cf_in,
                clock_fc_out,
                data_fc_out,
				data_out_mcu,
				data_in_mcu,
				clk_mcu,
                // outputs to smart media
                ale,
                cle,
                reb,
                web,
                wpb,
                io

	);
  
  input      pwronresetb;
  input	     clock48;
  input	     rcvin;
  input	     vpin;
  input	     vmin;
  inout	     data_cf_in;

  input       card_ready;

 // MCU I/F 
  output   data_out_mcu;
  output   clk_mcu;
  input    data_in_mcu;
  output     vmo;
  output     vpo;
  output     usboen;
  output     suspend;
  output     clock_fc_out;
  inout     data_fc_out;
  //output     usbclock;
  output             ale;
  output             cle;
  output             reb;
  output             web;
  output             wpb;
  input              gpiopin0;
  input              gpiopin1;
  input              gpiopin2;
  output             gpiopin3;
  output             gpiopin4;
  output             gpiopin5;
  output             gpiopin6;
  output             gpiopin7;
  inout     [7:0]    io;
wire      mcclock;
wire[7:0] smart_rd_data;
wire[7:0] smart_wr_data;

 Uusb_dual  usb_mmc_sm (
                // inputs from bus
		.testmode( 1'b0),
		.testreset( 1'b0),
		.pwronresetb( pwronresetb),
                .clock48( clock48),
                .rcvin(rcvin),
                .vpin(vpin),
                .vmin(vmin),
                .dataout_dat_in(dataout_dat_in),
                .dataout_dat_out(dataout_dat_out),
                .dataout_dat_enable(dataout_dat_enable),
                .card_ready(card_ready),
                .smart_rd_data(smart_rd_data),
                .vmo(vmo),
                .vpo(vpo),            // plus out
                .usboen(usboen), // oe for usb bits
                .suspend(suspend),
                .disablebus(disablebus),
				//for mcu I/F
                .data_in(data_in_mcu),
				.data_out(data_out_mcu),
				.clk_mcu(clk_mcu),
                .clock_fc_out(clock_fc_out_out),
                .datain_cmd_in(datain_cmd_in),
                .datain_cmd_out(datain_cmd_out),
                .datain_cmd_enable(datain_cmd_enable),
                .mcclock_out(mcclock),
                .mcclock(mcclock),
                .ale(ale_out),
                .cle(cle_out),
                .reb(reb_out),
                .web(web_out),
				//.usbclock(usbclock),
                .wpb(wpb_out),
				.gpiopin0(gpiopin0),
				.gpiopin1(gpiopin1),
				.gpiopin2(gpiopin2),
				.gpiopin3(gpiopin3),
				.gpiopin4(gpiopin4),
				.gpiopin5(gpiopin5),
				.gpiopin6(gpiopin6),
				.gpiopin7(gpiopin7),
				//.getstatusmmc(getstatusmmc),  rha 11.29
				//.multi_getdata(multi_getdata),  rha 11.29
				//.cmd_transmit(cmd_transmit),  rha 11.29
				//.data_receive(data_receive),  rha 11.29
				//.data_transmit(data_transmit),  rha 11.29
				//.status_receive(status_receive),  rha 11.29
                .out_enable(out_enable),
                .smart_wr_data(smart_wr_data)
                );

 mmc_tri_bus u0_tri_bus (
                .out_enable(dataout_dat_enable),
                .data_in(dataout_dat_in),
                .io(data_cf_in),
                .data_out(dataout_dat_out)
              );

 mmc_tri_bus u1_tri_bus (
                .out_enable(datain_cmd_enable),
                .data_in(datain_cmd_in),
                .io(data_fc_out),
                .data_out(datain_cmd_out)
              );

 tri_bus u2_tri_bus (
                .out_enableb(~out_enable),
                .smart_wr_data( smart_wr_data),
                .io( io),
                .smart_rd_data( smart_rd_data)
              );

 tri_signal u3_tri_bus (
                .out_enableb(disablebus),
                .data_out( ale_out),
                .io( ale)
              );

 tri_signal u4_tri_bus (
                .out_enableb(disablebus),
                .data_out( cle_out),
                .io( cle)
              );

 tri_signal u6_tri_bus (
                .out_enableb(disablebus),
                .data_out( reb_out),
                .io( reb)
              );

 tri_signal u7_tri_bus (
                .out_enableb(disablebus),
                .data_out( web_out),
                .io( web)
              );

 tri_signal u8_tri_bus (
                .out_enableb(disablebus),
                .data_out( wpb_out),
                .io( wpb)
              );

 tri_signal u10_tri_bus (
                .out_enableb(disablebus),
                .data_out( clock_fc_out_out),
                .io( clock_fc_out)
              );

endmodule