ufifo3rd.v

USBRTL电路的VHDL和Verilog代码

module Ufifo3rd(
		 usbclock,
		 syncreset,
		 fiford,
		 fifowrdata,
		 fiforddata
		 );
  input			 usbclock;
  input			 syncreset; 
  input			 fiford;
  
  input [15:0]	 fifowrdata;
  output [7:0]  fiforddata;
 
  reg  rdaddr;
  

  always @(posedge usbclock)
    begin
      if (syncreset)
	  rdaddr <= 'h0;
      else
	        rdaddr <= (fiford) ? rdaddr + 1'b1 : rdaddr;
    end // always @ (posedge usbclock)
  
  wire [7:0] fiforddata = (rdaddr == 1'b0) ? fifowrdata[15:8] : fifowrdata[7:0];

  
endmodule // devfifo