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📄 usienrzo.v

📁 USBRTL电路的VHDL和Verilog代码
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/******************************************
	Filename: 	sienrzo.v 1.13
******************************************/

/*
The sienrzo module does the NRZi Output encoding including
bit stuffing.  It also generates the usb output enable which
has an async flop to be sure we don't drive during reset.
If a bit gets stuffed, then nextxmitdata goes low for one
clock - nextxmitdata does the throttling of the next bit.
*/

module Usienrzo
	(
	// inputs
                testmode,
                testreset,
		usbclock,
		syncreset,
                usbreset,
		xmitactive,	// essentially turns on output
		xmitidle,	// sends idle after se0
		xmitdata,
		xmitse0,
		cpusignalresume,

	// outputs
		nextxmitdata,
		vpo,
		vmo,
		usboen
	);

`include "Usienrzodef.v"

  input         testmode;
  input         testreset;
  input	usbclock;
  input	syncreset;
  input	usbreset; // synopsys sync_set_reset "usbreset"
  input	 xmitactive;
  input	 xmitidle;
  input	 xmitdata;
  input	 xmitse0;
  input  cpusignalresume;

 output	nextxmitdata;
  output	 vpo;
  output	 vmo;
  output usboen;

reg	nextxmitdata;
reg	vpo;
reg	vmo;
wire	usboe;

reg	[7:0]	nrzost, nextnrzost;

wire	nrzozero = ~xmitdata;
wire	usboen = ~usboe;

// special aysnc flop logic for usboen 
wire    rstn;
assign  rstn = (testmode)? testreset : ~syncreset;
dffr asyncflop (
	.q (usboe),
	.d ((xmitactive || cpusignalresume)),
	.clk (usbclock),
	.rstn (rstn)
	);

always @(posedge usbclock)
begin
	if (cpusignalresume)	// we are causing a remote wakeup
	begin
		vpo <= 1'b0;
		vmo <= 1'b1;
	end
	else if (xmitse0)
	begin
		vpo <= 1'b0;
		vmo <= 1'b0;
	end
	else if (xmitidle)
	begin
		vpo <= 1'b1;
		vmo <= 1'b0;
	end
	else if ((nrzost == NRZOSTUFF) || nrzozero)
	begin
		vpo <= ~vpo;	// toggle
		vmo <= vpo;	// keep opposite of vpo
	end
	else
	begin
		vpo <= vpo;	// leave alone
		vmo <= ~vpo;	// keep opposite of vpo
	end
end

// state machine for syncing to the rcv transition edges

always @(posedge usbclock)
begin
	nrzost <= nextnrzost;
end

always @(nrzost or usbreset or xmitactive or xmitidle or xmitse0 or nrzozero)
begin
	if (usbreset)
	begin
		nextxmitdata = 1'b0;
		nextnrzost = NRZOIDLE;
	end
	else
		case (nrzost)	// synopsys parallel_case full_case
			NRZOIDLE:
			begin
				if (xmitactive && ~xmitidle)	// must leave idle with a 0
				begin
					nextnrzost = NRZOONE0;
					nextxmitdata = 1'b1;
				end
				else
				begin
					nextnrzost = NRZOIDLE;
					nextxmitdata = 1'b0;
				end
			end
			NRZOONE0:
			begin
			        nextxmitdata = 1'b1;
				if (xmitidle || ~xmitactive)
				    nextnrzost = NRZOIDLE;
				else if (xmitse0 || nrzozero)
				    nextnrzost = NRZOONE0;
				else
				    nextnrzost = NRZOONE1;	// must have been a 1
			end
			NRZOONE1:
			begin
				nextxmitdata = 1'b1;
				if (xmitidle || ~xmitactive)
				    nextnrzost = NRZOIDLE;
				else if (xmitse0 || nrzozero)
				    nextnrzost = NRZOONE0;
				else
				    nextnrzost = NRZOONE2;	// must have been a 1
			end
			NRZOONE2:
			begin
				nextxmitdata = 1'b1;
				if (xmitidle || ~xmitactive)
				    nextnrzost = NRZOIDLE;
				else if (xmitse0 || nrzozero)
				    nextnrzost = NRZOONE0;
				else
				    nextnrzost = NRZOONE3;	// must have been a 1
			end
			NRZOONE3:
			begin
				nextxmitdata = 1'b1;
				if (xmitidle || ~xmitactive)
				    nextnrzost = NRZOIDLE;
				else if (xmitse0 || nrzozero)
				    nextnrzost = NRZOONE0;
				else
				    nextnrzost = NRZOONE4;	// must have been a 1
			end
			NRZOONE4:
			begin
				nextxmitdata = 1'b1;
				if (xmitidle || ~xmitactive)
				    nextnrzost = NRZOIDLE;
				else if (xmitse0 || nrzozero)
				    nextnrzost = NRZOONE0;
				else
				    nextnrzost = NRZOONE5;	// must have been a 1
			end
			NRZOONE5:
			begin
				if (xmitidle || ~xmitactive)
				begin
					nextxmitdata = 1'b1;
					nextnrzost = NRZOIDLE;
				end
				else if (xmitse0 || nrzozero)
				begin
					nextxmitdata = 1'b1;
					nextnrzost = NRZOONE0;
				end
				else
				begin
					nextxmitdata = 1'b0;		// don't advance, I'm sending stuff bit next
					nextnrzost = NRZOSTUFF;	// must have been a 1
				end
			end
			NRZOSTUFF:
			begin
				nextxmitdata = 1'b1;
				nextnrzost = NRZOONE0;	// doing mandatory transition, see what's next
			end
	endcase
end

// make the ascii version of the nrzo state
// synopsys translate_off
reg [8*10:1]	nrzostate;
always @(nrzost)
case (nrzost)
	NRZOIDLE : nrzostate = "NRZOIDLE";
	NRZOONE0 : nrzostate = "NRZOONE0";
	NRZOONE1 : nrzostate = "NRZOONE1";
	NRZOONE2 : nrzostate = "NRZOONE2";
	NRZOONE3 : nrzostate = "NRZOONE3";
	NRZOONE4 : nrzostate = "NRZOONE4";
	NRZOONE5 : nrzostate = "NRZOONE5";
	NRZOSTUFF : nrzostate = "NRZOSTUFF";
endcase
// synopsys translate_on

endmodule

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